第一篇：多功能數(shù)字鐘課程設(shè)計(jì)整點(diǎn)報(bào)時(shí)與鬧鐘功能VHDL代碼

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity timkeeper is

Port(up,setpin,upclk,settime,run : in std_logic;

a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0);

result: out std_logic);end timkeeper;

architecture Behavioral of timkeeper is

component h_m_s_time port（clk0,clk1,ce : in std_logic;

sec0,sec1 : buffer std_logic_vector(3 downto 0);

lock : in std_logic_vector(2 downto 0);

up : in std_logic;min0,min1 : buffer std_logic_vector(3 downto 0);hour0,hour1 : buffer std_logic_vector(3 downto 0);ov : out std_logic);end component;component date port（clk0,clk1,ce : in std_logic;

lock : in std_logic_vector(2 downto 0);

up : in std_logic;

mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);

date0,date1 : buffer std_logic_vector(3 downto 0);

ov : out std_logic);

end component;component month_year port（clk0,clk1,ce : in std_logic;

lock : in std_logic_vector(2 downto 0);

up : in std_logic;

mon0,mon1 : buffer std_logic_vector(3 downto 0);

year0,year1 : buffer std_logic_vector(3 downto 0));end component;component LED_disp port（lock : in std_logic_vector(2 downto 0);

sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);

date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);

a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0));end component;component alarm Port（hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);

settime,run : in std_logic;

result : out std_logic);end component;

signal Tlock:std_logic_vector(2 downto 0);signal Tsecond_wave:std_logic;signal Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1:std_logic_vector(3 downto 0);signal Tdate0,Tdate1,Tmon0,Tmon1,Tyear0,Tyear1:std_logic_vector(3 downto 0);signal Tovday,Tovmonth:std_logic;signal vcc:std_logic;begin vcc<='1';process(setpin)begin

if rising_edge(setpin)then

Tlock<=Tlock+'1';

end if;

end process;

u2:h_m_s_time port map(Tsecond_wave,upclk,vcc,Tsec0,Tsec1,Tlock,up，Tmin0,Tmin1,Thour0,Thour1,Tovday);u3:date port map(Tovday,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1，Tdate0,Tdate1,Tovmonth);u4:month_year port map(Tovmonth,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1);u5:LED_disp port map(Tlock,Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,Tdate0，Tdate1,Tmon0,Tmon1,Tyear0,Tyear1,a0,a1,b0,b1,c0,c1);u6:alarm port map(Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,settime,run ,result);end Behavioral;

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity alarm is

Port(hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);

settime,run : in std_logic;

result : out std_logic);end alarm;

architecture Behavioral of alarm is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);begin p0:process(settime)

begin

if settime='1'then

dhour1<=hour1;

dhour0<=hour0;

dmin1<=min1;

dmin0<=min0;

dsec1<=sec1;

dsec0<=sec0;

end if;

end process p0;p1:process(run)

begin if run='1'then

if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then

result<='1';

else result<='0';

end if;else result<='0';end if;

end process p1;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity date is

Port(clk0,clk1,ce : in std_logic;

lock : in std_logic_vector(2 downto 0);

up : in std_logic;

mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);

date0,date1 : buffer std_logic_vector(3 downto 0);

ov : out std_logic);end date;

architecture Behavioral of date is signal tempy0:std_logic_vector(1 downto 0);signal tempy1,clk:std_logic;signal Td0,Td1:std_logic_vector(3 downto 0);begin tempy0<=year0(1 downto 0);tempy1<=year1(0);Td0<=date0;Td1<=date1;u1:process(lock,clk0,clk1)

begin

if(lock=“000” or lock=“001”)then clk<=clk0;

else clk<=clk1;

end if;

end process u1;

u2:process(clk,ce)

begin

if rising_edge(clk)then

if(ce='1')then

if(lock=“000”)or(lock=“001”)or(lock=“100” and up='1')then

if(mon0=“0010” and mon1=“0000”)then

Feb_add_day(Td0,Td1,tempy0,tempy1,date0,date1);

elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and or(mon0=“0101” and mon1=“0000”)or(mon0=“0111” and mon1=“0000”)

mon1=“0000”)

or(mon0=“1000” and mon1=“0000”)or(mon0=“0000”and mon1=“0001”)or(mon0=“0010” and mon1=“0001”))then

oddmonth_add_day(Td0,Td1,date0,date1);

else evenmonth_add_day(Td0,Td1,date0,date1);

end if;

end if;

if(lock=“100” and up='0')then

if(mon0=“0010” and mon1=“0000”)then

Feb_sub_day(Td0,Td1,tempy0,tempy1,date0,date1);

elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0101” and mon1=“0000”)or

(mon0=“0111” and mon1=“0000”)or(mon0=“1000” and mon1=“0000”)or(mon0=“0000” and mon1=“0001”)or(mon0=“0010”

and mon1=“0001”))then

oddmonth_sub_day(Td0,Td1,date0,date1);

else evenmonth_sub_day(Td0,Td1,date0,date1);

end if;

end if;

end if;

end if;

end process u2;

u3:process(ce)

begin

if rising_edge(clk)then

if(lock/=“000” and lock/=“001”)then

ov<='0';

elsif(ce='1')then

if(mon0=“0010” and mon1=“0000”)then

if((tempy1='0' and tempy0=“00”)or(tempy1='1' and tempy0=“10”))then

if(date0=“1001” and date1=“0010”)then

ov<='1';

else ov<='0';

end if;

elsif(date0=“1000” and date1=“0010”)then ov<='1';else ov<='0';end if;

elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0010” and mon1=“0000”)

or(mon0=“0111” and mon1=“0000”)or(mon0=“1000” or(mon0=“0000” and mon1=“0001”)

or(mon0=“0010” and mon1=“0001”))then

if(date0=“0001” and date1=“0011”)then

ov<='1';

else ov<='0';

end if;

elsif(date0=“0000” and date1=“0011”)then

ov<='1';

else ov<='0';

end if;

end if;

end if;

end process u3;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;

and

mon1=“0000”)use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity h_m_s_time is

Port(clk0,clk1,ce : in std_logic;

sec0,sec1 : buffer std_logic_vector(3 downto 0);

lock : in std_logic_vector(2 downto 0);

up : in std_logic;

min0,min1 : buffer std_logic_vector(3 downto 0);

hour0,hour1 : buffer std_logic_vector(3 downto 0);

ov : out std_logic);end h_m_s_time;

architecture Behavioral of h_m_s_time is signal Ts0,Ts1,Tm0,Tm1,Th0,Th1:std_logic_vector(3 downto 0);signal clk:std_logic;begin

Ts0<=sec0;Ts1<=sec1;Tm0<=min0;Tm1<=min1;Th0<=hour0;Th1<=hour1;u1: process(lock,clk0,clk1)

begin

if(lock=“000” or lock=“001”)then

clk<=clk0;

else clk<=clk1;

end if;

end process u1;

u2: process(clk,lock)

begin

if rising_edge(clk)then

if(ce='1')then

if(lock=“000”)or(lock=“001”)or(lock=“111” and up='1')then

addsec_addmin(Ts0,Ts1,sec0,sec1);

end if;

if(lock=“111” and up='0')then

subsec_submin(Ts0,Ts1,sec0,sec1);

end if;

if(lock=“000” or lock=“001”)then

if(sec0=“1001” and sec1=“0101”)then

addsec_addmin(Tm0,Tm1,min0,min1);

end if;

if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”)then

addhour(Th0,Th1,hour0,hour1);

end if;

if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”

and hour0=“0011” and hour1=“0010”)then

ov<='1';

else ov<='0';

end if;

end if;

if(lock=“110” and up='1')then

addsec_addmin(Tm0,Tm1,min0,min1);

end if;

if(lock=“101” and up='0')then

subsec_submin(Tm0,Tm1,min0,min1);

end if;

if(lock=“101” and up='1')then

addhour(Th0,Th1,hour0,hour1);

end if;

if(lock=“101” and up='0')then

subhour(Th0,Th1,hour0,hour1);

end if;

end if;

end if;

end process u2;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity LED_disp is

Port(lock : in std_logic_vector(2 downto 0);

sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);

date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);

a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0));end LED_disp;

architecture Behavioral of LED_disp is begin process(lock,sec0,sec1,min0,min1,hour0,hour1,date0,date1,mon0,mon1,year0,year1)

begin

if(lock=“000”)then

a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;

end if;

if(lock=“000”)then

a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;

end if;

if(lock=“001”)then

a0<=date0;a1<=date1;b0<=mon0;b1<=mon1;c0<=year0;c1<=year1;

end if;

if(lock=“101”)then

a0<=“0000”;a1<=“0000”;b0<=“0000”;b1<=“0000”;c0<=hour0;c1<=hour1;

end if;

if(lock=“110”)then

a0<=“0000”;a1<=“0000”;b0<=min0;b1<=min1;c0<=“0000”;c1<=“0000”;

end if;

if(lock=“111”)then

a0<=sec0;a1<=sec1;b0<=“0000”;b1<=“0000”;c0<=“0000”;c1<=“0000”;

end if;

if(lock=“010”)then a0<=“0000”;a1<=“0000”;b0<=“0000”;b1<=“0000”;c0<=year0;c1<=year1;end if;if(lock=“011”)then

a0<=“0000”;a1<=“0000”;b0<=mon0;b1<=mon1;c0<=“0000”;c1<=“0000”;

end if;

if(lock=“100”)then

a0<=date0;a1<=date1;b0<=“0000”;b1<=“0000”;c0<=“0000”;c1<=“0000”;

end if;

end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity month_year is

Port(clk0,clk1,ce : in std_logic;

lock : in std_logic_vector(2 downto 0);

up : in std_logic;

mon0,mon1 : buffer std_logic_vector(3 downto 0);

year0,year1 : buffer std_logic_vector(3 downto 0));end month_year;

architecture Behavioral of month_year is signal Ty0,Ty1,Tm0,Tm1:std_logic_vector(3 downto 0);signal clk:std_logic;begin

Ty0<=year0;Ty1<=year1;Tm0<=mon0;Tm1<=mon1;u1: process(lock,clk0,clk1)

begin

if(lock=“000” or lock=“001”)then

clk<=clk0;

else clk<=clk1;

end if;

end process u1;u2:process(clk,ce)begin if rising_edge(clk)then

if(ce='1')then

if(lock=“000”)or(lock=“001”)or(lock=“011” and up='1')then

add_month(Tm0,Tm1,mon0,mon1);

end if;

if(lock=“011” and up='0')then

sub_month(Tm0,Tm1,mon0,mon1);

end if;

if(lock=“000” or lock=“001”)then

if(mon0=“0010” and mon1=“0001”)then

add_year(Ty0,Ty1,year0,year1);

end if;

end if;

if(lock=“010” and up='1')then

add_year(Ty0,Ty1,year0,year1);

end if;

if(lock=“010” and up='0')then

sub_year(Ty0,Ty1,year0,year1);

end if;

end if;

end if;

end process u2;

end Behavioral;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

package pac is

procedure add_year(oldyear0,oldyear1:in std_logic_vector;

signal newyear0:out std_logic_vector;

signal newyear1:out std_logic_vector);procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;

signal newmonth0:out std_logic_vector;

signal newmonth1:out std_logic_vector);procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;

signal newmonth0:out std_logic_vector;

signal newmonth1:out std_logic_vector);procedure sub_year(oldyear0,oldyear1:in std_logic_vector;

signal newyear0:out std_logic_vector;

signal newyear1:out std_logic_vector);procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;

ty0:in std_logic_vector(1 downto 0);

ty1:in std_logic;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector);procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;

ty0:in std_logic_vector(1 downto 0);

ty1:in std_logic;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector);procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector);procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector);procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector);procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector);procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;

signal newtime0:out std_logic_vector;

signal newtime1:out std_logic_vector);procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;

signal newtime0:out std_logic_vector;

signal newtime1:out std_logic_vector);procedure addhour(oldhour0,oldhour1:in std_logic_vector;

signal newhour0:out std_logic_vector;

signal newhour1:out std_logic_vector);procedure subhour(oldhour0,oldhour1:in std_logic_vector;

signal newhour0:out std_logic_vector;

signal newhour1:out std_logic_vector);end pac;package body pac IS procedure add_year(oldyear0,oldyear1:in std_logic_vector;

signal newyear0:out std_logic_vector;

signal newyear1:out std_logic_vector)is

begin

if(oldyear0=“1001” and oldyear1/=“1001”)then

newyear0<=“0000”;newyear1<=oldyear1+'1';

else newyear0<=oldyear0+'1';

end if;if oldyear0=“1001” and oldyear1=“1001” then newyear0<=“0000”;

newyear1<=“0000”;end if;end add_year;

procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;

signal newmonth0:out std_logic_vector;

signal newmonth1:out std_logic_vector)is

begin

if oldmonth0=“0010” and oldmonth1=“0001” then newmonth0<=“0001”;

newmonth1<=“0000”;

elsif oldmonth0=“1001” then newmonth0<=“0000”;

newmonth1<=oldmonth1+'1';else

newmonth0<=oldmonth0+'1';end if;end add_month;procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;

signal newmonth0:out std_logic_vector;signal newmonth1: out std_logic_vector)is begin

if oldmonth0=“0001”and oldmonth1=“0000”then

newmonth0<=“0010”;newmonth1<=“0001”;

elsif oldmonth0=“0000” and oldmonth1=“0001” then

newmonth0<=“1001”;newmonth1<= oldmonth1-'1';else newmonth0<=oldmonth0-'1';end if;if oldmonth0=“0000” and oldmonth1=“0000”then

newmonth0<=“0010”;newmonth1<=“0001”;

end if;

end sub_month;procedure sub_year(oldyear0,oldyear1:in std_logic_vector;signal newyear0: out std_logic_vector;signal newyear1: out std_logic_vector)is

begin if oldyear0=“0000”then

if oldyear1=“0000”then

newyear1<=“1001”;else newyear1<= oldyear1-'1';end if;newyear0<=“1001”;else newyear0<=oldyear0-'1';end if;end sub_year;procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;

Ty0:in std_logic_vector(1 downto 0);

Ty1:in std_logic;

signal newday0: out std_logic_vector;

signal newday1: out std_logic_vector)is

begin

if oldday0=“1000”and oldday1=“0010”then

if((Ty1='0' and Ty0=“00”)or(ty1='1' and ty0=“10”))then

newday0<=oldday0 +'1';else newday0<=“0001”;newday1<=“0000”;end if;elsif oldday0=“1001” and oldday1=“0010”then

newday0<=“0001”;newday1<=“0000”;elsif oldday0=“1001” then

newday0<=“0000”;newday1<=oldday1+'1';else newday0<=oldday0+'1';end if;end Feb_add_day;

procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;

Ty0:in std_logic_vector(1 downto 0);

Ty1:in std_logic;

signal newday0: out std_logic_vector;

signal newday1: out std_logic_vector)is

begin

if(oldday0=“0000” or oldday0=“0001”)and oldday1=“0000”then

if((Ty1='0' and Ty0=“00”)or(ty1='1' and ty0=“10”))then

newday0<=“1001”;newday1<=“0010”;

else newday0<=“1000”;newday1<=“0010”;

end if;

elsif oldday0=“0000” and oldday1/=“0000”then

newday0<=“1001”;newday1<=oldday1-'1';else newday0<=oldday0-'1';end if;end Feb_sub_day;procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;

signal newday0: out std_logic_vector;

signal newday1: out std_logic_vector)is

begin

if(oldday0=“0001” and oldday1=“0011”)then

newday0<=“0001”;newday1<=“0000”;

elsif oldday0=“1001”then

newday0<=“0000”;newday1<=oldday1+'1';

else newday0<= oldday0+'1';

end if;

end oddmonth_add_day;procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;

signal newday0: out std_logic_vector;

signal newday1: out std_logic_vector)is

begin

if(oldday0=“0001” or oldday0=“0000”)and oldday1=“0000” then

newday0<=“0001”;newday1<=“0011”;

elsif oldday0=“0000” and oldday1/=“0000” then

newday0<=“1001”;newday1<=oldday1-'1';

else newday0<= oldday0-'1';

end if;

end oddmonth_sub_day;procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;

signal newday0: out std_logic_vector;

signal newday1: out std_logic_vector)is

begin

if oldday0=“0000” and oldday1=“0011” then newday0<=“0001”;

newday1<=“0000”;

elsif oldday0=“1001”then

newday0<=“0000”;

newday1<=oldday1+'1';

else newday0<=oldday0+'1';

end if;

end evenmonth_add_day;procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector)is begin

if(oldday0=“0000” or oldday0=“0001”)and oldday1=“0000”then

newday0<=“0000”;

newday1<=“0011”;elsif oldday0=“0000” and oldday1/=“0000”

then newday0<=“1001”;

newday1<=oldday1-'1';else

newday0<=oldday0-'1';

end if;end

evenmonth_sub_day;

procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;

signal newtime0:out std_logic_vector;

signal newtime1:out std_logic_vector)is

begin

if

(oldtime0=“1001”)then

newtime0<=“0000”;

if(oldtime1=“0101”)then

newtime1<=“0000”;

else newtime1<=oldtime1+'1';

end if;

else newtime0<=oldtime0+'1';

end if;

end addsec_addmin;procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;

signal newtime0:out std_logic_vector;

signal newtime1:out std_logic_vector)is begin

if(oldtime0=“0000”)then

newtime0<=“1001”;

if(oldtime1=“0000”)then

newtime1<=“0101”;

else newtime1<=oldtime1-'1';

end if;

else newtime0<=oldtime0-'1';

end if;

end

subsec_submin;procedure addhour(oldhour0,oldhour1:in std_logic_vector;

signal newhour0:out std_logic_vector;

signal newhour1:out std_logic_vector)is begin

if(oldhour0=“1001”)then

newhour0<=“0000”;

newhour1<=oldhour1+'1';

else newhour0<=oldhour0+'1';

end if;

if oldhour0=“0011” and oldhour1=“0010”then

newhour0<=“0000”;newhour1<=“0000”;

end if;

end

addhour;procedure subhour(oldhour0,oldhour1:in std_logic_vector;

signal newhour0:out std_logic_vector;

signal newhour1:out std_logic_vector)is begin if oldhour0=“0000” then

newhour1<=oldhour1-'1';newhour0<=“1001”;

else newhour0<=oldhour0-'1';

end if;

if oldhour0=“0000” and oldhour1=“0000”then

newhour0<=“0011”;newhour1<=“0010”;

end if;

end

subhour;end pac;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity second_wave is

Port(f1000 : in std_logic;

second_wave1 : buffer std_logic);end second_wave;

architecture Behavioral of second_wave is signal cnt:std_logic_vector(8 downto 0);begin

process(f1000,cnt)

begin

if rising_edge(f1000)then

if(cnt=“111110011”)then

cnt<=“000000000”;second_wave1<=not second_wave1;

else cnt<=cnt+'1';

end if;

end if;

end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity settime is

Port(hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);

mytime,run : in std_logic;

result : out std_logic);end settime;

architecture Behavioral of settime is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);begin p0:process(mytime)

begin

if mytime='1'then

dhour1<=hour1;

dhour0<=hour0;

dmin1<=min1;

dmin0<=min0;

dsec1<=sec1;

dsec0<=sec0;

end if;

end process p0;p1:process(run)

begin if run='1'then

if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then

result<='1';

else result<='0';

end if;else result<='0';end if;

end process p1;end Behavioral;

第二篇：多功能數(shù)字鐘課程設(shè)計(jì)VHDL代碼書(shū)上程序改

library ieee;use ieee.std_logic_1164.all;entity clock is port(clk1hz:in std_logic;--1hz脈沖--clk100:in std_logic;--100hz脈沖--weekclk:in std_logic;--星期調(diào)整脈沖--start_stop:in std_logic;--秒表啟動(dòng)/停止控制--reset:in std_logic;--秒表復(fù)位--adclk:in std_logic;--校時(shí)脈沖--setselect:in std_logic;--調(diào)整位選擇脈沖--mode:in std_logic;--功能選擇脈沖--showdate:in std_logic;--日期顯示--dis:out std_logic_vector(23 downto 0);--顯示輸出--glisten:out std_logic_vector(5 downto 0);--閃爍指示--weekout:out std_logic_vector(3 downto 0);--星期輸出--qh:out std_logic--整點(diǎn)報(bào)時(shí)--);end clock;architecture arch of clock is component adjust

port（adclk: in std_logic;

data_in: out std_logic_vector(7 downto 0));end component;component control

port（setclk: in std_logic;

setlap: out std_logic_vector(1 downto 0);

mode: in std_logic;

module: out std_logic_vector(2 downto 0));end component;component weekcounter

port（clk: in std_logic;

clk2: in std_logic;

q: out std_logic_vector(3 downto 0));end component;component stopwatch

port（clk: in std_logic;

reset: in std_logic;

start_stop: in std_logic;

centsec: out std_logic_vector(7 downto 0);

sec: out std_logic_vector(7 downto 0);

min: out std_logic_vector(7 downto 0));end component;component h_m_s_count

port（clk: in std_logic;

set: in std_logic;

setlap: in std_logic_vector(1 downto 0);

d:in std_logic_vector(7 downto 0);

sec:out std_logic_vector(7 downto 0);

min:out std_logic_vector(7 downto 0);

hour:out std_logic_vector(7 downto 0);

qh:out std_logic;

qc: out std_logic);end component;component y_m_d_count

port（clk: in std_logic;

set: in std_logic;

setlap: in std_logic_vector(1 downto 0);

data_in: in std_logic_vector(7 downto 0);

day: out std_logic_vector(7 downto 0);

month: out std_logic_vector(7 downto 0);

year: out std_logic_vector(7 downto 0));end component;component display

port（module: in std_logic_vector(2 downto 0);

showdate:in std_logic;

clk:in std_logic;

setlap:in std_logic_vector(1 downto 0);

watch: in std_logic_vector(23 downto 0);

time:in std_logic_vector(23 downto 0);

date:in std_logic_vector(23 downto 0);

dis: out std_logic_vector(23 downto 0);

glisten:out std_logic_vector(5 downto 0));end component;signal data_in,mcentsec,msec,mmin,ssec,smin,shour,sdate,smonth,syear:std_logic_vector(7 downto 0);signal setlap:std_logic_vector(1 downto 0);signal module:std_logic_vector(2 downto 0);signal qc:std_logic;signal watch,time,date:std_logic_vector(23 downto 0);begin u1:adjust port map(adclk,data_in);u2:control port map(setselect,setlap,mode,module);u3:stopwatch port map(clk100,reset,start_stop,mcentsec,msec,mmin);u4:h_m_s_count port map(clk1hz,module(1),setlap,data_in,ssec,smin,shour,qh,qc);u5:y_m_d_count port map(qc,module(2),setlap,data_in,sdate,smonth,syear);u6:display port map(module,showdate,clk1hz,setlap,watch,time,date,dis,glisten);u7:weekcounter port map(qc,weekclk,weekout);watch<=mmin&msec&mcentsec;time<=shour&smin&ssec;date<=syear&smonth&sdate;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity adjust is

port（adclk: in std_logic;

data_in: out std_logic_vector(7 downto 0));end adjust;architecture arch of adjust is signal temp2,temp1:std_logic_vector(3 downto 0);begin process(adclk)begin if rising_edge(adclk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else

temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;end if;end if;data_in<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity control is

port（setclk: in std_logic;--調(diào)整脈沖--

setlap: out std_logic_vector(1 downto 0);--調(diào)整位選擇脈沖--

mode: in std_logic;--功能選擇脈沖--

module: out std_logic_vector(2 downto 0)--功能輸出--);end control;architecture arch of control is signal ssetlap:std_logic_vector(1 downto 0);signal s:std_logic_vector(3 downto 0);begin process(mode,setclk)begin if mode='1'then ssetlap<=“00”;elsif rising_edge(setclk)then if ssetlap=“10”then ssetlap<=“00”;else ssetlap<=ssetlap+'1';end if;end if;end process;setlap<=ssetlap;process(mode)begin if rising_edge(mode)then case s is when“0001”=>s<=“0010”;when“0010”=>s<=“0100”;when“0100”=>s<=“1000”;when“1000”=>s<=“0001”;when others=>s<=“0010”;end case;end if;end process;module<=s(3 downto 1);end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter60 is

port（clk: in std_logic;--計(jì)數(shù)脈沖--

clr: in std_logic;--復(fù)位--

q: out std_logic_vector(7 downto 0);--計(jì)數(shù)值--

qc:out std_logic--進(jìn)位輸出--);end counter60;architecture arch of counter60 is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clr,clk)begin if clr='1'then temp1<=“0000”;temp2<=“0000”;elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else temp1<=temp1+'1';end if;if temp2=“0101” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter99 is

port（clk: in std_logic;--100vhz計(jì)數(shù)脈沖--

en: in std_logic;--計(jì)數(shù)使能--

clr: in std_logic;--復(fù)位--

q: out std_logic_vector(7 downto 0);--計(jì)數(shù)值--

qc: out std_logic--進(jìn)位--);end counter99;

architecture arch of counter99 is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clr,clk)begin if clr='1'then temp1<=“0000”;temp2<=“0000”;elsif rising_edge(clk)then if en='1' then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else

temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity daycounter is

port（clk: in std_logic;--計(jì)數(shù)脈沖--

set: in std_logic;--調(diào)整信號(hào)--

day_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--

day_out: out std_logic_vector(7 downto 0);--天輸出--

qc: out std_logic;--進(jìn)位--

day28: in std_logic;--該位為1表示該月為28天--

day29: in std_logic;--該位為1表示該月為29天--

day30: in std_logic;--該位為1表示該月為30天--

day31: in std_logic--該位為1表示該月為31天--);end daycounter;architecture arch of daycounter is signal temp1,temp2:std_logic_vector(3 downto 0);signal days:std_logic_vector(7 downto 0);begin days<=“00101000” when day28='1'else

“00101001”when day29='1'else

“00110000”when day30='1'else

“00110001”when day31='1'else

“00000000”;process(clk,set,day_in,days)begin if set='1' then temp2<=day_in(7 downto 4);temp1<=day_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else temp1<=temp1+'1';end if;if temp2&temp1=days then temp2<=“0000”;temp1<=“0001”;qc<='1';else qc<='0';end if;end if;end process;day_out<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity days_control is port（month: in std_logic_vector(7 downto 0);--月份--

year2: in std_logic;--年份高位數(shù)字bcd碼最低位--

year1: in std_logic_vector(1 downto 0);--年份低位數(shù)字bcd碼末兩位--

day28: out std_logic;--該位為1表示該月為28天--day29: out std_logic;--該位為1表示該月為29天--

day30: out std_logic;--該位為1表示該月為30天--

day31: out std_logic--該位為1表示該月為31天--);end days_control;architecture arch of days_control is begin process(month,year2,year1)begin case month is when “00000001”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000010”=>if(year2='0'and year1=“00”)or(year2='1'and year1=“10”)then

day28<='0';day29<='1';day30<='0';day31<='0';

else

day28<='1';day29<='0';day30<='0';day31<='0';

end if;when “00000011”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000100”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00000101”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000110”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00000111”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00001000”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00001001”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00010000”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00010001”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00010010”=>day28<='0';day29<='0';day30<='0';day31<='1';when others=>day28<='0';day29<='0';day30<='0';day31<='1';end case;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity display is

port（module: in std_logic_vector(2 downto 0);--功能選擇--

showdate:in std_logic;--顯示日期--

clk:in std_logic;--閃爍脈沖--

setlap:in std_logic_vector(1 downto 0);--閃爍位選擇--

watch: in std_logic_vector(23 downto 0);--秒表計(jì)數(shù)值輸入--

time:in std_logic_vector(23 downto 0);--時(shí)分秒計(jì)數(shù)值輸入--date:in std_logic_vector(23 downto 0);--年月日計(jì)數(shù)值輸入--

dis: out std_logic_vector(23 downto 0);--顯示輸出--

glisten:out std_logic_vector(5 downto 0)--閃爍輸出--);end display;architecture arch of display is begin process(module,showdate,watch,time,date)begin if showdate='1'then dis<=date;else case module is when“001”=>dis<=watch;when“010”=>dis<=time;when“100”=>dis<=date;when others=>dis<=time;end case;end if;end process;process(clk,module,setlap)begin if module=“010”or module=“100”then case setlap is when“00”=>glisten(1 downto 0)<=clk&clk;

glisten(5 downto 2)<=“0000”;when“01”=>glisten(3 downto 2)<=clk&clk;

glisten(5 downto 4)<=“00”;

glisten(1 downto 0)<=“00”;when“10”=>glisten(5 downto 4)<=clk&clk;

glisten(3 downto 0)<=“0000”;when others=>glisten<=“000000”;end case;else glisten<=“000000”;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity dmux is

port（set:in std_logic;--調(diào)整信號(hào)--

setlap: in std_logic_vector(1 downto 0);--調(diào)整位選擇--

d: in std_logic_vector(7 downto 0);--調(diào)整輸入--

set1:out std_logic;

set2:out std_logic;

set3:out std_logic;

q1: out std_logic_vector(7 downto 0);

q2: out std_logic_vector(7 downto 0);

q3: out std_logic_vector(7 downto 0));end dmux;architecture arch of dmux is begin process(set,setlap,d)begin if set='1' then case setlap is when“00”=>set1<='1';set2<='0';set3<='0';

q1<=d;when“01”=>set1<='0';set2<='1';set3<='0';

q2<=d;when“10”=>set1<='0';set2<='0';set3<='1';

q3<=d;when others=>set1<='0';set2<='0';set3<='0';end case;else set1<='0';set2<='0';set3<='0';end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity h_m_s_count is

port（clk: in std_logic;--1hz脈沖--

set: in std_logic;--調(diào)整信號(hào)--

setlap: in std_logic_vector(1 downto 0);--調(diào)整位選擇--

d:in std_logic_vector(7 downto 0);--調(diào)整輸入--

sec:out std_logic_vector(7 downto 0);--秒輸出--

min:out std_logic_vector(7 downto 0);--分輸出--

hour:out std_logic_vector(7 downto 0);--小時(shí)輸出--

qh:out std_logic;--整點(diǎn)報(bào)時(shí)--

qc: out std_logic--進(jìn)位--);end h_m_s_count;architecture arch of h_m_s_count is component sec_mincounter

port（clk: in std_logic;

set:in std_logic;

d:in std_logic_vector(7 downto 0);

q:out std_logic_vector(7 downto 0);

qc:out std_logic);end component;component hourcounter port（clk: in std_logic;

set:in std_logic;

d:in std_logic_vector(7 downto 0);

q: out std_logic_vector(7 downto 0);

qc:out std_logic);end component;component dmux

port（set:in std_logic;

setlap: in std_logic_vector(1 downto 0);

d: in std_logic_vector(7 downto 0);

set1:out std_logic;

set2:out std_logic;

set3:out std_logic;

q1: out std_logic_vector(7 downto 0);

q2: out std_logic_vector(7 downto 0);

q3: out std_logic_vector(7 downto 0));end component;signal secset,minset,hourset: std_logic;signal secin,minin,hourin:std_logic_vector(7 downto 0);signal qcsec,qcmin,qchour: std_logic;begin u1:dmux port map(set,setlap,d,secset,minset,hourset,secin,minin,hourin);u2:sec_mincounter port map(clk,secset,secin,sec,qcsec);u3:sec_mincounter port map(qcsec,minset,minin,min,qcmin);u4:hourcounter port map(qcmin,hourset,hourin,hour,qchour);qh<=qcmin;qc<=qchour;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity hourcounter is

port（clk: in std_logic;--計(jì)數(shù)脈沖--

set:in std_logic;--調(diào)整信號(hào)--

d:in std_logic_vector(7 downto 0);--調(diào)整時(shí)間--

q: out std_logic_vector(7 downto 0);--小時(shí)輸出--

qc:out std_logic--進(jìn)位--);end hourcounter;architecture arch of hourcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set)begin if set='1'then temp2<=d(7 downto 4);temp1<=d(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else

temp1<=temp1+'1';end if;if temp2=“0010” and temp1=“0100” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end process;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity monthcounter is

port（clk: in std_logic;--計(jì)數(shù)脈沖--

set: in std_logic;--調(diào)整信號(hào)--

month_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--

month_out: out std_logic_vector(7 downto 0);--月輸出--

qc: out std_logic--進(jìn)位--);end monthcounter;architecture arch of monthcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set,month_in)begin if set='1' then temp2<=month_in(7 downto 4);temp1<=month_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else

temp1<=temp1+'1';end if;if temp2=“0001”and temp1=“0010” then temp2<=“0000”;temp1<=“0001”;qc<='1';else qc<='0';end if;end if;end process;month_out<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity sec_mincounter is port（clk: in std_logic;--計(jì)數(shù)脈沖--

set:in std_logic;--調(diào)整信號(hào)--

d:in std_logic_vector(7 downto 0);--調(diào)整時(shí)間輸入--

q:out std_logic_vector(7 downto 0);--分和秒輸出--

qc:out std_logic--進(jìn)位--);end sec_mincounter;architecture arch of sec_mincounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set)begin if set='1'then temp2<=d(7 downto 4);temp1<=d(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else

temp1<=temp1+'1';end if;if temp2=“0101” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end process;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity stopwatch is port（clk: in std_logic;--100hz脈沖--

reset: in std_logic;--復(fù)位--

start_stop: in std_logic;--啟動(dòng)/停止--

centsec: out std_logic_vector(7 downto 0);--百分秒輸出，當(dāng)超過(guò)60分轉(zhuǎn)為秒--

sec: out std_logic_vector(7 downto 0);--秒輸出，當(dāng)超過(guò)60分轉(zhuǎn)為分--

min: out std_logic_vector(7 downto 0)--分輸出，當(dāng)超過(guò)60分轉(zhuǎn)為小時(shí)--);end stopwatch;architecture arch of stopwatch is component counter99 port（clk: in std_logic;

en: in std_logic;

clr: in std_logic;

q: out std_logic_vector(7 downto 0);

qc: out std_logic);end component;component counter60 port（clk: in std_logic;

clr: in std_logic;

q: out std_logic_vector(7 downto 0);

qc: out std_logic);end component;signal qc1,qc2,qc3,qc4,flag:std_logic;signal tcentsec,tsec,tmin,thour:std_logic_vector(7 downto 0);begin u1:counter99 port map(clk,start_stop,reset,tcentsec,qc1);u2:counter60 port map(qc1,reset,tsec,qc2);u3:counter60 port map(qc2,reset,tmin,qc3);u4:counter60 port map(qc3,reset,thour,qc4);process(qc3)begin if rising_edge(qc3)then flag<='1';end if;if flag='1' then centsec<=tsec;sec<=tmin;min<=thour;else centsec<=tcentsec;sec<=tsec;min<=tmin;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity weekcounter is

port（clk: in std_logic;--天脈沖--

clk2: in std_logic;--外部星期調(diào)整脈沖--

q: out std_logic_vector(3 downto 0)--星期輸出--);end weekcounter;architecture arch of weekcounter is signal temp:std_logic_vector(3 downto 0);signal cp:std_logic;begin cp<=clk or clk2;process begin wait until rising_edge(cp);if temp=“0111” then temp<=“0001”;else

temp<=temp+'1';end if;q<=temp;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity y_m_d_count is

port（clk: in std_logic;--計(jì)數(shù)脈沖--

set: in std_logic;--調(diào)整信號(hào)--

setlap: in std_logic_vector(1 downto 0);--調(diào)整位選擇--

data_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--

day: out std_logic_vector(7 downto 0);--日輸出--

month: out std_logic_vector(7 downto 0);--月輸出--

year: out std_logic_vector(7 downto 0)--年輸出--);end y_m_d_count;architecture arch of y_m_d_count is component daycounter

port（clk: in std_logic;

set: in std_logic;

day_in: in std_logic_vector(7 downto 0);

day_out: out std_logic_vector(7 downto 0);

qc: out std_logic;

day28: in std_logic;

day29: in std_logic;

day30: in std_logic;

day31: in std_logic);end component;component monthcounter

port（clk: in std_logic;

set: in std_logic;

month_in: in std_logic_vector(7 downto 0);

month_out: out std_logic_vector(7 downto 0);

qc: out std_logic);end component;component yearcounter

port（clk: in std_logic;

set: in std_logic;

year_in: in std_logic_vector(7 downto 0);

year_out: out std_logic_vector(7 downto 0));end component;component dmux

port（set:in std_logic;

setlap: in std_logic_vector(1 downto 0);

d: in std_logic_vector(7 downto 0);

set1:out std_logic;

set2:out std_logic;

set3:out std_logic;

q1: out std_logic_vector(7 downto 0);

q2: out std_logic_vector(7 downto 0);

q3: out std_logic_vector(7 downto 0));end component;component days_control

port（month: in std_logic_vector(7 downto 0);

year2: in std_logic;

year1: in std_logic_vector(1 downto 0);

day28: out std_logic;

day29: out std_logic;

day30: out std_logic;

day31: out std_logic);end component;signal dayset,monthset,yearset: std_logic;signal qcday,qcmonth: std_logic;signal dayin,monthin,yearin: std_logic_vector(7 downto 0);signal smonth,syear:std_logic_vector(7 downto 0);signal day28,day29,day30,day31:std_logic;begin u1:dmux port map(set,setlap,data_in,dayset,monthset,yearset,dayin,monthin,yearin);u2:daycounter port map(clk,dayset,dayin,day,qcday,day28,day29,day30,day31);u3:monthcounter port map(qcday,monthset,monthin,smonth,qcmonth);u4:yearcounter port map(qcmonth,yearset,yearin,syear);u8:days_control port map(smonth,syear(4),syear(1 downto 0),day28,day29,day30,day31);month<=smonth;year<=syear;

end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yearcounter is

port（clk: in std_logic;--計(jì)數(shù)脈沖--

set: in std_logic;--調(diào)整信號(hào)--

year_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--

year_out: out std_logic_vector(7 downto 0)--年輸出--);end yearcounter;architecture arch of yearcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set,year_in)begin if set='1' then temp2<=year_in(7 downto 4);temp1<=year_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else

temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;end if;end if;end process;year_out<=temp2&temp1;end arch;

第三篇：用狀態(tài)機(jī)實(shí)現(xiàn)的EDA多功能數(shù)字鐘課程設(shè)計(jì)VHDL代碼

設(shè)計(jì)并實(shí)現(xiàn)具有一定功能的數(shù)字鐘

1、該數(shù)字鐘可以實(shí)現(xiàn)3個(gè)功能：計(jì)時(shí)功能、整點(diǎn)報(bào)時(shí)功能和重置時(shí)間功能，因此有3個(gè)功能：計(jì)時(shí)、重置時(shí)間、復(fù)位。

2、對(duì)所有設(shè)計(jì)的小系統(tǒng)能夠正確分析；

3、基于VHDL語(yǔ)言描述系統(tǒng)的功能；

4、在quartus 2環(huán)境中編譯通過(guò)；

5、仿真通過(guò)并得到正確的波形；

6、給出相應(yīng)的設(shè)計(jì)報(bào)告。

其中計(jì)時(shí)模塊有4部分構(gòu)成：秒計(jì)時(shí)器（second）、分計(jì)時(shí)器(minute)、時(shí)計(jì)時(shí)器(hour)、日計(jì)時(shí)器(date)、月計(jì)時(shí)器（mouth）、年計(jì)時(shí)器（year）

1）秒計(jì)時(shí)器（second）是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，秒計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，秒計(jì)時(shí)器置數(shù)，置s1的值。clk為驅(qū)動(dòng)秒計(jì)時(shí)器的時(shí)鐘，sec為秒計(jì)時(shí)器的輸出，ensec為秒計(jì)時(shí)器的進(jìn)位信號(hào)，作為下一級(jí)的時(shí)鐘輸入信號(hào)。

2）分計(jì)時(shí)器（minute）是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，分計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，分計(jì)時(shí)器置數(shù)，置m1的值。clkm為驅(qū)動(dòng)分計(jì)時(shí)器工作的時(shí)鐘，與ensec相連接；min為分計(jì)時(shí)器的輸出；enmin為分計(jì)時(shí)器的進(jìn)位信號(hào)，作為下一級(jí)的時(shí)鐘輸入信號(hào)。

3）時(shí)計(jì)時(shí)器（hour）是由一個(gè)24進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，時(shí)計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，時(shí)計(jì)時(shí)器置數(shù)，置h1的值。clkh為驅(qū)動(dòng)時(shí)計(jì)時(shí)器工作的時(shí)鐘，與enmin相連接；hour為時(shí)計(jì)時(shí)器的輸出；enhour為時(shí)計(jì)時(shí)器的進(jìn)位信號(hào)，作為下一級(jí)的時(shí)鐘輸入信號(hào)。

4）日計(jì)時(shí)器（date1）是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，星期計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，星期計(jì)時(shí)器置數(shù)，置d1的值。clkd為驅(qū)動(dòng)星期計(jì)時(shí)器工作的時(shí)鐘，與enhour相連接；date為日計(jì)時(shí)器的輸出，endate為分計(jì)時(shí)器的進(jìn)位信號(hào)，作為下一級(jí)的時(shí)鐘輸入信號(hào)，由于月份的天數(shù)存在天數(shù)不同，閏年2月的天數(shù)為28天等情況，還設(shè)計(jì)了一個(gè)潤(rùn)年判別器，準(zhǔn)確顯示時(shí)間。

5）月計(jì)時(shí)器（mouth）是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，星期計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，星期計(jì)時(shí)器置數(shù)，置mou1的值，clkmou為驅(qū)動(dòng)星期計(jì)時(shí)器工作的時(shí)鐘，與enday相連接；mou為日計(jì)時(shí)器的輸出，enmou為分計(jì)時(shí)器的進(jìn)位信號(hào)，作為下一級(jí)的時(shí)鐘輸入信號(hào)。6）計(jì)時(shí)器（year）是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，星期計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，星期計(jì)時(shí)器置數(shù)，置y1的值，clky為驅(qū)動(dòng)星期計(jì)時(shí)器工作的時(shí)鐘，與enmou相連接；year為日計(jì)時(shí)器的輸出。VHDL程序

1、屏幕切換模塊

運(yùn)用狀態(tài)機(jī)進(jìn)行屏幕切換，分別顯示年月日，以及時(shí)分秒 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity mux3 is

Port(clk,Reset,sel : in std_logic;

int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--rst must

a1,a2,a3,a4,a5,a6: out std_logic_vector(3 downto 0));end mux3;

architecture Behavioral of mux3 is

TYPE states IS(st0, st1, st2, st3, st4, st5, st6, st7);

SIGNAL STX: states;

begin

COM1 : PROCESS(STX,int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12)

BEGIN--決定轉(zhuǎn)換狀態(tài)的進(jìn)程

CASE STX IS

WHEN st0 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;

WHEN st1 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;

WHEN st2 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;

WHEN st3 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;

WHEN st4 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;

WHEN st5 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;

WHEN st6 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;

WHEN st7 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;

WHEN OTHERS => NULL;

END CASE;

END PROCESS COM1;REG: PROCESS(clk,Reset,sel)

--主控時(shí)序進(jìn)程

BEGIN

IF Reset = '1' THEN

STX<= st0;

--異步復(fù)位

ELSIF clk='1' AND clk'EVENT THEN

if sel='1' then

CASE STX IS

WHEN st0=>STX<=st1;

WHEN st1=>STX<=st2;

WHEN st2=>STX<=st3;

WHEN st3=>STX<=st4;

WHEN st4=>STX<=st5;

WHEN st5=>STX<=st6;

WHEN st6=>STX<=st7;

WHEN st7=>STX<=st0;

END CASE;

END IF;

END if;END PROCESS;

2、顯示切換程序 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity mux1 is

Port(clk,ina,inb,sel,Reset : in std_logic;

result : out std_logic);end mux1;

architecture Behavioral of mux1 is

TYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7);

SIGNAL STX:state;begin REG1: PROCESS(ina,inb,STX)

BEGIN

CASE STX IS

WHEN st0=>result<=ina;

WHEN st1=>result<=ina;

WHEN st2=>result<=inb;

WHEN st3=>result<=inb;

WHEN st4=>result<=inb;

WHEN st5=>result<=inb;

WHEN st6=>result<=inb;

WHEN st7=>result<=inb;

END CASE;

END PROCESS;REG2:PROCESS(clk,sel,Reset)BEGIN IF(Reset='1')THEN

STX<=st0;ELSIF(clk'EVENT AND clk='1')THEN

if sel='1' then CASE STX IS WHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;

END CASE;END IF;end if;END PROCESS REG2;

end Behavioral;

3、置數(shù)操作模塊

運(yùn)用狀態(tài)機(jī)，進(jìn)行置數(shù)操作 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity mux is

Port(clk,ina,inb,sel,Reset : in std_logic;

r1,r2,r3,r4,r5,r6 : out std_logic);end mux;

architecture Behavioral of mux is TYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7);

SIGNAL STX:state;begin PROCESS(ina,inb,STX)BEGIN CASE STX IS WHEN st0=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';WHEN st1=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';WHEN st2=>r1<='0';r2<='0';r3<='0';r4<='0';r5<='0';r6<=inb;WHEN st3=>r1<='0';r2<='0';r3<='0';r4<='0';r5<=inb;r6<='0';WHEN st4=>r1<='0';r2<='0';r3<='0';r4<=inb;r5<='0';r6<='0';WHEN st5=>r1<='0';r2<='0';r3<=inb;r4<='0';r5<='0';r6<='0';WHEN st6=>r1<='0';r2<=inb;r3<='0';r4<='0';r5<='0';r6<='0';WHEN st7=>r1<=inb;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';END CASE;END PROCESS;PROCESS(clk,sel,Reset)BEGIN IF(Reset='1')THEN STX<=st0;ELSIF(clk'EVENT AND clk='1')THEN if sel='1' then CASE STX IS WHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;

END CASE;END IF;end if;END PROCESS;end Behavioral;end Behavioral;

4、秒顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity secute1 is

Port(clkm,set,reset : in std_logic;

sec2,sec1 : inout std_logic_vector(3 downto 0);

ensec : out std_logic);end secute1;

architecture Behavioral of secute1 is

begin

Process(clkm,reset,set)

Begin

If reset='1' then sec2<=“0000”;sec1<=“0000”;

Elsif set='1' then sec2<=“0101”;sec1<=“1000”;

Elsif(clkm'event and clkm='1')then

if sec2=“0101” AND sec1=“1001” then sec2<=“0000”;sec1<=“0000”;ensec<='1';

elsif sec1=“1001” then sec2<=sec2+'1';sec1<=“0000”;ensec<='0';

else sec1<=sec1+'1';ensec<='0';

end if;end if;End process;end Behavioral;

5、分顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity minute1 is

Port(clkm,set,reset : in std_logic;

min2,min1 : inout std_logic_vector(3 downto 0);

enmin : out std_logic);end minute1;

architecture Behavioral of minute1 is

begin

Process(clkm,reset,set)

Begin

If reset='1' then min2<=“0000”;min1<=“0000”;

Elsif set='1' then min2<=“0101”;min1<=“1000”;

Elsif(clkm'event and clkm='1')then

if min2=“0101” AND min1=“1001” then min2<=“0000”;min1<=“0000”;enmin<='1';

elsif min1=“1001” then min2<=min2+'1';min1<=“0000”;enmin<='0';

else min1<=min1+'1';enmin<='0';

end if;end if;End process;end Behavioral;

6、小時(shí)顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity hour1 is

Port(clkh,set,reset: in std_logic;

hor2,hor1 : inout std_logic_vector(3 downto 0);

enhour : out std_logic);end hour1;

architecture Behavioral of hour1 is

begin Process(clkh,reset,set)

Begin

If reset='1' then hor2<=“0000”;hor1<=“0000”;

Elsif set='1' then hor2<=“0010”;hor1<=“0011”;

Elsif(clkh'event and clkh='1')then

if hor2=“0010” AND hor1=“0011” then hor2<=“0000”;hor1<=“0000”;enhour<='1';

elsif hor1=“1001” then hor2<=hor2+'1';hor1<=“0000”;enhour<='0';

else hor1<=hor1+'1';enhour<='0';

end if;

end if;End process;end Behavioral;

7、日顯示模塊（已加入閏年判斷功能）library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity date1 is

Port(clkd,set : in std_logic;

dat2,dat1 : inout std_logic_vector(3 downto 0);

endate : out std_logic);end date1;

architecture Behavioral of date1 is

begin

Process(clkd,set)

Begin

if set='1' then dat2<=“0010”;dat1<=“1000”;

Elsif(clkd'event and clkd='1')then

if dat2=“0011” AND dat1=“0000” then dat2<=“0000”;dat1<=“0001”;endate<='1';elsif dat1=“1001” then dat2<=dat2+'1';dat1<=“0000”;endate<='0';

else dat1<=dat1+'1';endate<='0';

end if;end if;End process;end Behavioral;

8、月顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity month1 is

Port(clkn,set: in std_logic;

mon2,mon1 : inout std_logic_vector(3 downto 0);

enmon : out std_logic);end month1;

architecture Behavioral of month1 is

begin

Process(clkn,set)

Begin

if set='1' then mon2<=“0000”;mon1<=“0110”;

Elsif(clkn'event and clkn='1')then

if mon2=“0001” AND mon1=“0010” then mon2<=“0000”;mon1<=“0001”;enmon<='1';

elsif mon1=“1001” then mon2<=mon2+'1';mon1<=“0000”;enmon<='0';

else mon1<=mon1+'1';enmon<='0';

end if;end if;End process;

9、年顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity yearth1 is

Port(clkn,set: in std_logic;

year2,year1 : inout std_logic_vector(3 downto 0);

enyear : out std_logic);end yearth1;

architecture Behavioral of yearth1 is

begin

Process(clkn,set)

Begin

if set='1' then year2<=“0001”;year1<=“0001”;

Elsif(clkn'event and clkn='1')then

if year2=“1001” AND year1=“1001” then year2<=“0000”;year1<=“0001”;

elsif year1=“1001” then year2<=year2+'1';year1<=“0000”;enyear<='0';

else year1<=year1+'1';enyear<='0';

end if;end if;

end Behavioral;