第一篇：用狀態(tài)機(jī)實(shí)現(xiàn)的EDA多功能數(shù)字鐘課程設(shè)計(jì)VHDL代碼
設(shè)計(jì)并實(shí)現(xiàn)具有一定功能的數(shù)字鐘
1、該數(shù)字鐘可以實(shí)現(xiàn)3個(gè)功能：計(jì)時(shí)功能、整點(diǎn)報(bào)時(shí)功能和重置時(shí)間功能，因此有3個(gè)功能：計(jì)時(shí)、重置時(shí)間、復(fù)位。
2、對(duì)所有設(shè)計(jì)的小系統(tǒng)能夠正確分析；
3、基于VHDL語(yǔ)言描述系統(tǒng)的功能；
4、在quartus 2環(huán)境中編譯通過(guò)；
5、仿真通過(guò)并得到正確的波形；
6、給出相應(yīng)的設(shè)計(jì)報(bào)告。
其中計(jì)時(shí)模塊有4部分構(gòu)成：秒計(jì)時(shí)器（second）、分計(jì)時(shí)器(minute)、時(shí)計(jì)時(shí)器(hour)、日計(jì)時(shí)器(date)、月計(jì)時(shí)器（mouth）、年計(jì)時(shí)器（year）
1）秒計(jì)時(shí)器（second）是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，秒計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，秒計(jì)時(shí)器置數(shù)，置s1的值。clk為驅(qū)動(dòng)秒計(jì)時(shí)器的時(shí)鐘，sec為秒計(jì)時(shí)器的輸出，ensec為秒計(jì)時(shí)器的進(jìn)位信號(hào)，作為下一級(jí)的時(shí)鐘輸入信號(hào)。
2）分計(jì)時(shí)器（minute）是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，分計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，分計(jì)時(shí)器置數(shù)，置m1的值。clkm為驅(qū)動(dòng)分計(jì)時(shí)器工作的時(shí)鐘，與ensec相連接；min為分計(jì)時(shí)器的輸出；enmin為分計(jì)時(shí)器的進(jìn)位信號(hào)，作為下一級(jí)的時(shí)鐘輸入信號(hào)。
3）時(shí)計(jì)時(shí)器（hour）是由一個(gè)24進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，時(shí)計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，時(shí)計(jì)時(shí)器置數(shù)，置h1的值。clkh為驅(qū)動(dòng)時(shí)計(jì)時(shí)器工作的時(shí)鐘，與enmin相連接；hour為時(shí)計(jì)時(shí)器的輸出；enhour為時(shí)計(jì)時(shí)器的進(jìn)位信號(hào)，作為下一級(jí)的時(shí)鐘輸入信號(hào)。
4）日計(jì)時(shí)器（date1）是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，星期計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，星期計(jì)時(shí)器置數(shù)，置d1的值。clkd為驅(qū)動(dòng)星期計(jì)時(shí)器工作的時(shí)鐘，與enhour相連接；date為日計(jì)時(shí)器的輸出，endate為分計(jì)時(shí)器的進(jìn)位信號(hào)，作為下一級(jí)的時(shí)鐘輸入信號(hào)，由于月份的天數(shù)存在天數(shù)不同，閏年2月的天數(shù)為28天等情況，還設(shè)計(jì)了一個(gè)潤(rùn)年判別器，準(zhǔn)確顯示時(shí)間。
5）月計(jì)時(shí)器（mouth）是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，星期計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，星期計(jì)時(shí)器置數(shù)，置mou1的值，clkmou為驅(qū)動(dòng)星期計(jì)時(shí)器工作的時(shí)鐘，與enday相連接；mou為日計(jì)時(shí)器的輸出，enmou為分計(jì)時(shí)器的進(jìn)位信號(hào)，作為下一級(jí)的時(shí)鐘輸入信號(hào)。6）計(jì)時(shí)器（year）是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有清0、置數(shù)和計(jì)數(shù)功能。其中reset為清0信號(hào)，當(dāng)reset為0時(shí)，星期計(jì)時(shí)器清0；set 為置數(shù)信號(hào)，當(dāng)set為0時(shí)，星期計(jì)時(shí)器置數(shù)，置y1的值，clky為驅(qū)動(dòng)星期計(jì)時(shí)器工作的時(shí)鐘，與enmou相連接；year為日計(jì)時(shí)器的輸出。VHDL程序
1、屏幕切換模塊
運(yùn)用狀態(tài)機(jī)進(jìn)行屏幕切換，分別顯示年月日，以及時(shí)分秒 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux3 is
Port(clk,Reset,sel : in std_logic;
int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--rst must
a1,a2,a3,a4,a5,a6: out std_logic_vector(3 downto 0));end mux3;
architecture Behavioral of mux3 is
TYPE states IS(st0, st1, st2, st3, st4, st5, st6, st7);
SIGNAL STX: states;
begin
COM1 : PROCESS(STX,int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12)
BEGIN--決定轉(zhuǎn)換狀態(tài)的進(jìn)程
CASE STX IS
WHEN st0 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st1 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st2 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st3 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st4 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;
WHEN st5 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st6 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN st7 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;
WHEN OTHERS => NULL;
END CASE;
END PROCESS COM1;REG: PROCESS(clk,Reset,sel)
--主控時(shí)序進(jìn)程
BEGIN
IF Reset = '1' THEN
STX<= st0;
--異步復(fù)位
ELSIF clk='1' AND clk'EVENT THEN
if sel='1' then
CASE STX IS
WHEN st0=>STX<=st1;
WHEN st1=>STX<=st2;
WHEN st2=>STX<=st3;
WHEN st3=>STX<=st4;
WHEN st4=>STX<=st5;
WHEN st5=>STX<=st6;
WHEN st6=>STX<=st7;
WHEN st7=>STX<=st0;
END CASE;
END IF;
END if;END PROCESS;
2、顯示切換程序 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux1 is
Port(clk,ina,inb,sel,Reset : in std_logic;
result : out std_logic);end mux1;
architecture Behavioral of mux1 is
TYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7);
SIGNAL STX:state;begin REG1: PROCESS(ina,inb,STX)
BEGIN
CASE STX IS
WHEN st0=>result<=ina;
WHEN st1=>result<=ina;
WHEN st2=>result<=inb;
WHEN st3=>result<=inb;
WHEN st4=>result<=inb;
WHEN st5=>result<=inb;
WHEN st6=>result<=inb;
WHEN st7=>result<=inb;
END CASE;
END PROCESS;REG2:PROCESS(clk,sel,Reset)BEGIN IF(Reset='1')THEN
STX<=st0;ELSIF(clk'EVENT AND clk='1')THEN
if sel='1' then CASE STX IS WHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;
END CASE;END IF;end if;END PROCESS REG2;
end Behavioral;
3、置數(shù)操作模塊
運(yùn)用狀態(tài)機(jī)，進(jìn)行置數(shù)操作 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity mux is
Port(clk,ina,inb,sel,Reset : in std_logic;
r1,r2,r3,r4,r5,r6 : out std_logic);end mux;
architecture Behavioral of mux is TYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7);
SIGNAL STX:state;begin PROCESS(ina,inb,STX)BEGIN CASE STX IS WHEN st0=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';WHEN st1=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';WHEN st2=>r1<='0';r2<='0';r3<='0';r4<='0';r5<='0';r6<=inb;WHEN st3=>r1<='0';r2<='0';r3<='0';r4<='0';r5<=inb;r6<='0';WHEN st4=>r1<='0';r2<='0';r3<='0';r4<=inb;r5<='0';r6<='0';WHEN st5=>r1<='0';r2<='0';r3<=inb;r4<='0';r5<='0';r6<='0';WHEN st6=>r1<='0';r2<=inb;r3<='0';r4<='0';r5<='0';r6<='0';WHEN st7=>r1<=inb;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';END CASE;END PROCESS;PROCESS(clk,sel,Reset)BEGIN IF(Reset='1')THEN STX<=st0;ELSIF(clk'EVENT AND clk='1')THEN if sel='1' then CASE STX IS WHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;
END CASE;END IF;end if;END PROCESS;end Behavioral;end Behavioral;
4、秒顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity secute1 is
Port(clkm,set,reset : in std_logic;
sec2,sec1 : inout std_logic_vector(3 downto 0);
ensec : out std_logic);end secute1;
architecture Behavioral of secute1 is
begin
Process(clkm,reset,set)
Begin
If reset='1' then sec2<=“0000”;sec1<=“0000”;
Elsif set='1' then sec2<=“0101”;sec1<=“1000”;
Elsif(clkm'event and clkm='1')then
if sec2=“0101” AND sec1=“1001” then sec2<=“0000”;sec1<=“0000”;ensec<='1';
elsif sec1=“1001” then sec2<=sec2+'1';sec1<=“0000”;ensec<='0';
else sec1<=sec1+'1';ensec<='0';
end if;end if;End process;end Behavioral;
5、分顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity minute1 is
Port(clkm,set,reset : in std_logic;
min2,min1 : inout std_logic_vector(3 downto 0);
enmin : out std_logic);end minute1;
architecture Behavioral of minute1 is
begin
Process(clkm,reset,set)
Begin
If reset='1' then min2<=“0000”;min1<=“0000”;
Elsif set='1' then min2<=“0101”;min1<=“1000”;
Elsif(clkm'event and clkm='1')then
if min2=“0101” AND min1=“1001” then min2<=“0000”;min1<=“0000”;enmin<='1';
elsif min1=“1001” then min2<=min2+'1';min1<=“0000”;enmin<='0';
else min1<=min1+'1';enmin<='0';
end if;end if;End process;end Behavioral;
6、小時(shí)顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity hour1 is
Port(clkh,set,reset: in std_logic;
hor2,hor1 : inout std_logic_vector(3 downto 0);
enhour : out std_logic);end hour1;
architecture Behavioral of hour1 is
begin Process(clkh,reset,set)
Begin
If reset='1' then hor2<=“0000”;hor1<=“0000”;
Elsif set='1' then hor2<=“0010”;hor1<=“0011”;
Elsif(clkh'event and clkh='1')then
if hor2=“0010” AND hor1=“0011” then hor2<=“0000”;hor1<=“0000”;enhour<='1';
elsif hor1=“1001” then hor2<=hor2+'1';hor1<=“0000”;enhour<='0';
else hor1<=hor1+'1';enhour<='0';
end if;
end if;End process;end Behavioral;
7、日顯示模塊（已加入閏年判斷功能）library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity date1 is
Port(clkd,set : in std_logic;
dat2,dat1 : inout std_logic_vector(3 downto 0);
endate : out std_logic);end date1;
architecture Behavioral of date1 is
begin
Process(clkd,set)
Begin
if set='1' then dat2<=“0010”;dat1<=“1000”;
Elsif(clkd'event and clkd='1')then
if dat2=“0011” AND dat1=“0000” then dat2<=“0000”;dat1<=“0001”;endate<='1';elsif dat1=“1001” then dat2<=dat2+'1';dat1<=“0000”;endate<='0';
else dat1<=dat1+'1';endate<='0';
end if;end if;End process;end Behavioral;
8、月顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity month1 is
Port(clkn,set: in std_logic;
mon2,mon1 : inout std_logic_vector(3 downto 0);
enmon : out std_logic);end month1;
architecture Behavioral of month1 is
begin
Process(clkn,set)
Begin
if set='1' then mon2<=“0000”;mon1<=“0110”;
Elsif(clkn'event and clkn='1')then
if mon2=“0001” AND mon1=“0010” then mon2<=“0000”;mon1<=“0001”;enmon<='1';
elsif mon1=“1001” then mon2<=mon2+'1';mon1<=“0000”;enmon<='0';
else mon1<=mon1+'1';enmon<='0';
end if;end if;End process;
9、年顯示模塊 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity yearth1 is
Port(clkn,set: in std_logic;
year2,year1 : inout std_logic_vector(3 downto 0);
enyear : out std_logic);end yearth1;
architecture Behavioral of yearth1 is
begin
Process(clkn,set)
Begin
if set='1' then year2<=“0001”;year1<=“0001”;
Elsif(clkn'event and clkn='1')then
if year2=“1001” AND year1=“1001” then year2<=“0000”;year1<=“0001”;
elsif year1=“1001” then year2<=year2+'1';year1<=“0000”;enyear<='0';
else year1<=year1+'1';enyear<='0';
end if;end if;
end Behavioral;
第二篇：EDA課程設(shè)計(jì)——多功能數(shù)字鐘
哈爾濱工業(yè)大學(xué)(威海)電子學(xué)課程設(shè)計(jì)報(bào)告
帶有整點(diǎn)報(bào)時(shí)的數(shù)字鐘設(shè)計(jì)與制作
姓名: 蔣棟棟 班級(jí): 0802503 學(xué)號(hào): 080250331 指導(dǎo)教師:
井巖
目錄
一、課程設(shè)計(jì)的性質(zhì)、目的和任務(wù)????????????3
二、課程設(shè)計(jì)基本要求?????????????????3
三、設(shè)計(jì)課題要求???????????????????3
四、課程設(shè)計(jì)所需要儀器????????????????4
五、設(shè)計(jì)步驟?????????????????????4
1、整體設(shè)計(jì)框圖???????????????????4
2、各個(gè)模塊的設(shè)計(jì)與仿真???????????????4
2.1分頻模塊???????????????????????4
2.2計(jì)數(shù)器模塊??????????????????????6
2.3控制模塊??????????????????????10
2.4數(shù)碼管分配?????????????????????13
2.5顯示模塊??????????????????????14
2.6報(bào)時(shí)模塊??????????????????????16
六、調(diào)試中遇到的問(wèn)題及解決的方法???????????18
七、心得體會(huì)?????????????????????18
一、課程設(shè)計(jì)的性質(zhì)、目的和任務(wù)
創(chuàng)新精神和實(shí)踐能力二者之中，實(shí)踐能力是基礎(chǔ)和根本。這是由于創(chuàng)新基于實(shí)踐、源于實(shí)踐，實(shí)踐出真知，實(shí)踐檢驗(yàn)真理。實(shí)踐活動(dòng)是創(chuàng)新的源泉，也是人才成長(zhǎng)的必由之路。
通過(guò)課程設(shè)計(jì)的鍛煉，要求學(xué)生掌握電路的一般設(shè)計(jì)方法，具備初步的獨(dú)立設(shè)計(jì)能力，提高綜合運(yùn)用所學(xué)的理論知識(shí)獨(dú)立分析和解決問(wèn)題的能力，培養(yǎng)學(xué)生的創(chuàng)新精神。
二、課程設(shè)計(jì)基本要求
掌握現(xiàn)代大規(guī)模集成數(shù)字邏輯電路的應(yīng)用設(shè)計(jì)方法，進(jìn)一步掌握電子儀器的正確使用方法，以及掌握利用計(jì)算機(jī)進(jìn)行電子設(shè)計(jì)自動(dòng)化(EDA)的基本方法。
三、設(shè)計(jì)課題要求
（1）構(gòu)造一個(gè)24小時(shí)制的數(shù)字鐘。要求能顯示時(shí)、分、秒。（2）要求時(shí)、分、秒能各自獨(dú)立的進(jìn)行調(diào)整。
（3）能利用喇叭作整點(diǎn)報(bào)時(shí)。從59分50秒時(shí)開始報(bào)時(shí)，每隔一秒報(bào)時(shí)一秒，到達(dá)00分00秒時(shí)，整點(diǎn)報(bào)時(shí)。整點(diǎn)報(bào)時(shí)聲的頻率應(yīng)與其它的報(bào)時(shí)聲頻有明顯區(qū)別。
#設(shè)計(jì)提示（僅供參考）：（1）對(duì)頻率輸入的考慮
數(shù)字鐘內(nèi)所需的時(shí)鐘頻率有：基準(zhǔn)時(shí)鐘應(yīng)為周期一秒的標(biāo)準(zhǔn)信號(hào)。報(bào)時(shí)頻率可選用1KHz和2KHz左右(兩種頻率相差八度音，即頻率相差一倍)。另外，為防止按鍵反跳、抖動(dòng)，微動(dòng)開關(guān)輸入應(yīng)采用寄存器輸入形式，其時(shí)鐘應(yīng)為幾十赫茲。
（2）計(jì)時(shí)部分計(jì)數(shù)器設(shè)計(jì)的考慮 分、秒計(jì)數(shù)器均為模60計(jì)數(shù)器。
小時(shí)計(jì)數(shù)為模24計(jì)數(shù)器，同理可建一個(gè)24進(jìn)制計(jì)數(shù)器的模塊。（3）校時(shí)設(shè)計(jì)的考慮
數(shù)字鐘校準(zhǔn)有3個(gè)控制鍵：時(shí)校準(zhǔn)、分校準(zhǔn)和秒校準(zhǔn)。
微動(dòng)開關(guān)不工作，計(jì)數(shù)器正常工作。按下微動(dòng)開關(guān)后，計(jì)數(shù)器以8Hz頻率連續(xù)計(jì)數(shù)(若只按一下，則計(jì)數(shù)器增加一位)，可調(diào)用元件庫(kù)中的邏輯門建一個(gè)控制按鍵的模塊，即建立開關(guān)去抖動(dòng)電路(見書70頁(yè))。
（4）報(bào)時(shí)設(shè)計(jì)的考慮
可以將高頻時(shí)鐘分頻得到約2KHz和1KHz的音頻，作為數(shù)字鐘的報(bào)時(shí)頻率。當(dāng)電子鐘顯示XX：59：50時(shí)，數(shù)字鐘開始報(bào)時(shí)“DO“，持續(xù)一秒，而且每隔一秒報(bào)一下，直至顯示XX：00：00時(shí)報(bào)“DI”，持續(xù)一秒后停止。最后輸出至喇叭。應(yīng)調(diào)用元件庫(kù)中的邏輯門建一個(gè)控制報(bào)時(shí)的模塊。
（5）建一個(gè)七段譯碼的模塊
因在系統(tǒng)可編程器件實(shí)驗(yàn)箱上的數(shù)碼管沒有經(jīng)過(guò)譯碼，故要用AHDL語(yǔ)言寫一個(gè)七段譯碼的模塊，且應(yīng)考慮數(shù)碼管為共陽(yáng)極。數(shù)碼管上的點(diǎn)(D2、D4、D6)應(yīng)置Vcc。
四、課程設(shè)計(jì)所需要儀器
1、計(jì)算機(jī)一臺(tái)
2、quartusⅡ軟件
3、FPGA開發(fā)板
五、設(shè)計(jì)步驟
1、模塊介紹
（1）分頻模塊：產(chǎn)生1Hz、1KHz、2KHz頻率（2）計(jì)數(shù)器模塊：生成60進(jìn)制、24進(jìn)制計(jì)數(shù)器（3）控制模塊：按鍵控制、按鍵消抖
（4）顯示模塊：7段數(shù)碼管顯示器，分別顯示小時(shí)、分鐘、秒（5）報(bào)時(shí)模塊：進(jìn)行整點(diǎn)報(bào)時(shí)
2、各個(gè)模塊的設(shè)計(jì)與仿真
2.1分頻模塊
CLK晶振頻率50MHZ，分成2KHZ,1KHZ,1HZ的信號(hào)?；鶞?zhǔn)1HZ信號(hào)作為時(shí)鐘計(jì)時(shí)的秒計(jì)數(shù)時(shí)鐘信號(hào)；分頻的1KHZ,2KHZ信號(hào)用于報(bào)時(shí)電路的不同聲訊。
程序代碼：
library ieee;use ieee.std_logic_1164.all;entity fre is port(clk ,sel: in std_logic;clk1hz,clk1khz,clk2khz:out std_logic);end fre;architecture beh of fre is signal data1khz,data2khz,data1hz : std_logic := '0';begin clk1hz <= data1hz;clk1khz <= data1khz;clk2khz <= data2khz;clk1khz_pro : process(clk)--產(chǎn)生1khz信號(hào) variable cnt : integer range 0 to 24999;begin if clk'event and clk='1' then if cnt = 24999 then cnt := 0;data1khz <= not data1khz;else cnt := cnt + 1;end if;end if;end process clk1khz_pro;clk2khz_pro : process(clk)--variable cnt : integer range 0 to 12499;begin if clk'event and clk='1' then if cnt = 12499 then cnt := 0;data2khz <= not data2khz;else cnt := cnt + 1;end if;end if;end process clk2khz_pro;clk1hz_pro : process(data1khz)--variable cnt : integer range 0 to 499;begin if data1khz'event and data1khz='1' then if sel='0' then cnt:=0;else if cnt = 499 then cnt := 0;data1hz <= not data1hz;else cnt := cnt + 1;end if;end if;end if;end process clk1hz_pro;end beh;
輸入模塊電路圖：
產(chǎn)生2khz信號(hào) 產(chǎn)生1hz 信號(hào) 5 freclkclk1hzclk2khzinst selclk1khz2.2計(jì)數(shù)器模塊
由秒計(jì)數(shù)器，分計(jì)數(shù)器，時(shí)計(jì)數(shù)器組成了最基本的數(shù)字鐘計(jì)時(shí)電路，兩個(gè)六十進(jìn)制計(jì)數(shù)器與二十四進(jìn)制計(jì)數(shù)器組合構(gòu)成。
程序代碼：
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOGIC_ARITH.ALL;
entity shuzizhong is port(clk_change : in std_logic;s_en,m_en,h_en:in std_logic;sel:in std_logic;secout,minout,hourout :out std_logic;sl,sh,ml,mh,hl,hh:out std_logic_vector(3 downto 0);a:out std_logic_vector(15downto 0));end shuzizhong;architecture behav of shuzizhong is
signal low_rega,high_rega,low_regb,high_regb,low_regc,high_regc :std_logic_vector(3 downto 0):=“0000”;signal sout,mout,hout :std_logic :='0';begin--秒的60進(jìn)制進(jìn)制 counter_sec_l : process(clk_change,s_en)begin
sl<=low_rega;sh<=high_rega;ml<=low_regb;mh<=high_regb;hl<=low_regc;hh<=high_regc;6 if clk_change'event and clk_change='1' then if s_en='1' then if low_rega=“1001” then low_rega <= “0000”;else low_rega <= low_rega+'1';end if;end if;end if;end process counter_sec_l;counter_sec_h : process(clk_change,s_en,low_rega)begin if clk_change'event and clk_change='1' then if s_en='1' then if low_rega=“1001” then if high_rega =“0101”then high_rega <= “0000”;else high_rega <= high_rega+'1';end if;end if;end if;end if;end process counter_sec_h;sout <= '1' when low_rega=“1001” and high_rega=“0101” else '0';
----分鐘的60進(jìn)制設(shè)置 counter_min_l : process(clk_change,m_en)begin if clk_change'event and clk_change='1' then if m_en='1' then if sout='1'or sel='0' then if low_regb=“1001” then low_regb <= “0000”;else low_regb <= low_regb+'1';end if;end if;end if;end if;end process counter_min_l;counter_min_h : process(clk_change,m_en,low_regb)begin if clk_change'event and clk_change='1' then 7 if sout='1'or sel='0' then if m_en='1' then if low_regb=“1001” then
if high_regb =“0101”then
high_regb <= “0000”;else high_regb <= high_regb+'1';end if;end if;end if;end if;end if;end process counter_min_h;mout <= '1' when low_regb=“1001” and high_regb=“0101”and sout='1' else '0';--小時(shí)的24進(jìn)制設(shè)置 counter_hour_l : process(clk_change,h_en)begin if clk_change'event and clk_change='1' then if h_en='1' then if mout='1'or sel='0' then if low_regc=“1001”or hout='1' then low_regc <= “0000”;else low_regc <= low_regc+'1';end if;end if;end if;end if;end process counter_hour_l;counter_hour_h : process(clk_change,h_en,hout)begin if clk_change'event and clk_change='1' then if mout='1'or sel='0' then if h_en='1' then if hout='1' then high_regc<=“0000”;else if low_regc=“1001” then high_regc <= high_regc+'1';end if;end if;end if;8 end if;end if;end process counter_hour_h;hout <= '1' when low_regc=“0011” and high_regc=“0010” else '0';secout<=sout;minout<=mout;hourout<=hout;a<=high_regb&low_regb&high_rega&low_rega;end behav;
輸入模塊電路圖：
shuzizhongclk_changes_enm_enh_enselsecoutminouthouroutsl[3..0]sh[3..0]ml[3..0]mh[3..0]hl[3..0]hh[3..0]a[15..0]inst
2.3控制模塊
分五個(gè)狀態(tài)0狀態(tài)正常計(jì)時(shí)，按下按鍵進(jìn)入下一狀態(tài)開始調(diào)時(shí)模式1，按下按鍵進(jìn)入調(diào)秒模式2，按下按鍵進(jìn)入調(diào)分模式3，按下按鍵進(jìn)入調(diào)小時(shí)模式4.按下按鍵恢復(fù)正常計(jì)時(shí)模式。
程序代碼：
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity key_press is port(set ,mode: in std_logic;clk1khz,clk1hz: in std_logic;secout,minout: in std_logic;clk_change,clk2hz_en:out std_logic;sel,s_ce,m_ce,h_ce:out std_logic;s_en,m_en,h_en:out std_logic);end key_press;architecture beh of key_press is 9 signal key1,key2:std_logic;signal sce_reg, mce_reg ,hce_reg:std_logic;signal ssl,ssen,mmen,hhen:std_logic;signal con : integer range 0 to 4 :=0;--按鍵按下（延時(shí)）begin
key_press2 : process(set,clk1khz)variable cnt :integer range 0 to 999;begin if set='0' then if clk1khz'event and clk1khz='1'then if cnt=50 and set='0' then cnt :=cnt+1;key2 <= '1';else cnt:=cnt+1;key2 <= '0';end if;end if;else cnt:=0;key2<='0';end if;end process key_press2;key_press1 : process(mode,clk1khz)variable cnt :integer range 0 to 999;begin if mode='0' then if clk1khz'event and clk1khz='1'then if cnt=50 and mode='0' then cnt :=cnt+1;key1 <= '1';else cnt:=cnt+1;key1 <= '0';end if;end if;else cnt:=0;key1<='0';end if;end process key_press1;count : process(key1,key2)begin if key1'event and key1='1' then if con=4 then con<=0;else con<=con+1;end if;end if;10 end process count;con_pro : process(con)begin case con is when 0 => ssl<='1';sce_reg <= '0';ssen <='1';mce_reg <= '0';mmen <='1';hce_reg <= '0';hhen <='1';clk2hz_en <='0';when 1 => ssl<='0';sce_reg <= '0';ssen <='1';mce_reg <= '0';mmen <='1';hce_reg <= '0';hhen <='1';clk2hz_en <='1';when 2 => ssl<='0';sce_reg <= '1';ssen <='1';mce_reg <= '0';mmen <='0';hce_reg <= '0';hhen <='0';clk2hz_en <='1';when 3 => ssl<='0';sce_reg <= '0';ssen <='0';mce_reg <= '1';mmen <='1';hce_reg <= '0';hhen <='0';clk2hz_en <='1';when 4 => ssl<='0';sce_reg <= '0';ssen <='0';mce_reg <= '0';mmen <='0';hce_reg <= '1';hhen <='1';clk2hz_en <='1';when others => ssl<='0';sce_reg <= '0';ssen <='1';mce_reg <= '0';mmen <='1';hce_reg <= '0';hhen <='1';clk2hz_en <='0';end case;end process con_pro;sel_pro : process(ssl)begin case ssl is when '0'=> s_ce<=sce_reg;m_ce<=mce_reg;h_ce<=hce_reg;clk_change<=key2;when '1'=> s_ce<=ssen;11 m_ce<=mmen;h_ce<=hhen;clk_change<=clk1hz;when others=> s_ce<=ssen;m_ce<=secout;h_ce<=minout;clk_change<=clk1hz;end case;end process sel_pro;sel<=ssl;s_en<=ssen;m_en<=mmen;h_en<=hhen;end beh;
輸入模塊電路圖： key_presssetclk_changemodeclk2hz_enclk1khzselclk1hzs_cesecoutm_ceminouth_ces_enm_enh_eninst
2.4數(shù)碼管分配
程序代碼：
library ieee;use ieee.std_logic_1164.all;entity display is port(datain : in std_logic_vector(3 downto 0);dataout : out std_logic_vector(7 downto 0));end display;architecture duan of display is begin process(datain)begin case datain is 12 when “0000” => dataout <=“11000000”;--dp,g,f,e,d,c,b,a when “0001” => dataout <=“11111001”;when “0010” => dataout <=“10100100”;when “0011” => dataout <=“10110000”;when “0100” => dataout <=“10011001”;when “0101” => dataout <=“10010010”;when “0110” => dataout <=“10000010”;when “0111” => dataout <=“11111000”;when “1000” => dataout <=“10000000”;when “1001” => dataout <=“10010000”;when “1010” => dataout <=“10111111”;when “1011” => dataout <=“10000011”;when “1100” => dataout <=“10100111”;when “1101” => dataout <=“10100001”;when “1110” => dataout <=“10000110”;when “1111” => dataout <=“10001110”;when others => null;end case;end process;end;
輸入模塊電路圖：
displaydatain[3..0]dataout[7..0]inst
2.5顯示模塊
使用七段數(shù)碼管顯示小時(shí)、分鐘與秒
程序代碼：
library ieee;use ieee.std_logic_1164.all;entity scan is port(clk1khz : in std_logic;sl,sh,ml,mh,hl,hh : in std_logic_vector(3 downto 0);clk2hz_en : in std_logic;s_ce,m_ce,h_ce : in std_logic;en_out : out std_logic_vector(7 downto 0);13 dataout : out std_logic_vector(3 downto 0));end scan;architecture beh of scan is signal cnt : integer range 0 to 7;signal en : std_logic_vector(7 downto 0);signal clk2hz : std_logic;signal h_ce_reg,m_ce_reg,s_ce_reg : std_logic;begin h_ce_reg <= not h_ce;m_ce_reg <= not m_ce;s_ce_reg <= not s_ce;cnt_pro : process(clk1khz)begin if clk1khz'event and clk1khz='1' then if cnt = 7 then cnt <= 0;else cnt <= cnt + 1;end if;end if;end process cnt_pro;clk2hz_pro :process(clk1khz)variable c : integer range 0 to 499 := 0;begin if clk1khz'event and clk1khz='1' then if clk2hz_en ='1' then if c =499 then c := 0;clk2hz <= not clk2hz;else c := c + 1;end if;else clk2hz <= '0';end if;end if;end process clk2hz_pro;scan_pro : process(cnt,sl,sh,ml,mh,hl,hh)begin case cnt is when 0 => dataout <= sl;en <= “11111110”;when 1 => dataout <= sh;en <= “11111101”;when 2 => dataout <= ml;en <= “11110111”;when 3 => dataout <= mh;en <= “11101111”;when 4 => dataout <= hl;en <= “10111111”;14 when 5 => dataout <= hh;en <= “01111111”;when 6 => dataout <= “1010”;en <= “11111011”;when 7 => dataout <= “1010”;en <= “11011111”;when others => null;end case;end process scan_pro;
en_out <= en or((clk2hz & clk2hz)or(h_ce_reg & h_ce_reg))& clk2hz &((clk2hz & clk2hz)or(m_ce_reg & m_ce_reg))& clk2hz &((clk2hz & clk2hz)or(s_ce_reg & s_ce_reg));end beh;
輸入模塊電路圖：
scanclk1khzen_out[7..0]sl[3..0]dataout[3..0]sh[3..0]ml[3..0]mh[3..0]hl[3..0]hh[3..0]clk2hz_ens_cem_ceh_ceinst
2.6報(bào)時(shí)模塊
利用蜂鳴器進(jìn)行整點(diǎn)報(bào)時(shí)
程序代碼：
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOGIC_ARITH.ALL;--整點(diǎn)報(bào)時(shí) entity baoshi is port(clk1khz,clk2khz : in std_logic;a:in std_logic_vector(15 downto 0);sel:in std_logic;bell:out std_logic);end baoshi;architecture zhong of baoshi is signal c1,ring:std_logic;begin ring_bell :process(clk1khz,clk2khz)15 begin case a is when “***0” => c1<=clk1khz;when “***0” => c1<=clk1khz;when “***0” => c1<=clk1khz;when “***0” => c1<=clk1khz;when “***0” => c1<=clk1khz;when “***0” => c1<=clk2khz;when “***0” => c1<=clk2khz;when others => c1<='0';end case;end process ring_bell;
bs: process(c1)begin if sel='1' then if c1='1' then ring<='0';else ring<='1';end if;end if;end process bs;bell<=ring;
end zhong;
輸入模塊電路圖：
baoshiclk1khzbellclk2khza[15..0]selinst
整體模塊電路圖
displayshuzizhongs_enm_enh_enselclk_changes_enm_enh_enselsecoutminouthouroutsl[3..0]sh[3..0]ml[3..0]mh[3..0]hl[3..0]hh[3..0]setmodefreclkINPUTVCCINPUTVCCdata[3..0]datain[3..0]secoutminoutinst1scanclk1khzclk1khzsl[3..0]sh[3..0]ml[3..0]mh[3..0]hl[3..0]a[15..0]dataout[7..0]OUTPUTdataout[7..0]en_out[7..0]dataout[3..0]OUTPUTen_out[7..0]data[3..0]key_presssetclk1khzmodeclk1khzclk1hzsecoutminoutclk_changeclk2hz_ensels_cem_ceh_ces_enm_enh_eninst6s_enm_enh_enselinst7a[15..0]INPUTVCChh[3..0]clk2hz_ens_cem_ceh_ceinst4baoshiclk1khzclk2khza[15..0]selclk1khzbellclk2khza[15..0]sel++selclkclk1hzselclk1khzclk2khzinst2clk1khzclk2khzsecoutminoutOUTPUTbellinst
六、調(diào)試中遇到的問(wèn)題及解決的方法：
1、編程時(shí)，經(jīng)常導(dǎo)致語(yǔ)法錯(cuò)誤，如：“；”沒有寫上，變量類型沒有預(yù)先標(biāo)明，前后變量名字由于缺少一個(gè)或多一個(gè)字母而導(dǎo)致出錯(cuò)。解決辦法：對(duì)照錯(cuò)誤，認(rèn)真檢查程序，看哪個(gè)地方的標(biāo)點(diǎn)，變量沒有寫上或標(biāo)明。
2、進(jìn)行編譯或波形仿真時(shí)，經(jīng)常得到的不是預(yù)想中的結(jié)果。
解決辦法：將需要編譯或進(jìn)行仿真的實(shí)體文件置頂，經(jīng)檢錯(cuò)無(wú)誤后，進(jìn)行波形仿真，在仿真之前需要合理設(shè)置仿真結(jié)束時(shí)間和信號(hào)周期。
3、在控制時(shí)間的顯示的時(shí)候，由于變量太多多發(fā)現(xiàn)不能完全的控制住變量，導(dǎo)致顯示的時(shí)候出現(xiàn)了亂碼，數(shù)碼管顯示不正常 解決辦法：減少變量，仔細(xì)推敲，合理命名。
七、心得體會(huì)
一個(gè)多星期的課程設(shè)計(jì)讓我受益匪淺，也讓我真正明白理論與實(shí)踐相結(jié)合的重要性。通過(guò)具體實(shí)踐才能讓自己清楚哪些知識(shí)已經(jīng)掌握，哪些知識(shí)仍需鞏固加強(qiáng)。與此同時(shí)，我也對(duì)EDA以及VHDL語(yǔ)言有了進(jìn)一步了解，對(duì)于其結(jié)構(gòu)、語(yǔ)法、功能等認(rèn)識(shí)不少。當(dāng)然，我目前所做的還僅僅只是一些基本操作，要想真正將其融會(huì)貫通還需要今后更多的學(xué)習(xí)與實(shí)踐。雖然只是一個(gè)小設(shè)計(jì)，我卻也從中學(xué)到了不少設(shè)計(jì)流程和一些相關(guān)問(wèn)題。設(shè)計(jì)是一個(gè)十分嚴(yán)謹(jǐn)?shù)倪^(guò)程，容不得隨意和馬虎。要想快速而高效地完成一項(xiàng)設(shè)計(jì)，必須先有一個(gè)清晰明了的設(shè)計(jì)思路，設(shè)想好一個(gè)整體框架，然后在此基礎(chǔ)上，逐漸將各個(gè)部分功能進(jìn)行完善。在設(shè)計(jì)的過(guò)程中，也曾遇到不少困難，但正所謂堅(jiān)持就是勝利，要想取得成功，必須要有努力付出，這樣所取得的結(jié)果才更有意義。
第三篇：EDA實(shí)現(xiàn)多功能數(shù)字鐘
EDA實(shí)現(xiàn)多功能數(shù)字鐘
實(shí)
驗(yàn) 報(bào) 告
專業(yè)班級(jí)：
學(xué)生姓名：
學(xué)生學(xué)號(hào)：
目錄
一、內(nèi)容摘要
二、實(shí)驗(yàn)要求
三、各底層模塊設(shè)計(jì)
四、總體方案
五、心得體會(huì)
一、實(shí)驗(yàn)內(nèi)容
利用 QuartusII 軟件，結(jié)合所學(xué)的數(shù)字電路的知識(shí)設(shè)計(jì)一個(gè) 24 時(shí)多功能數(shù) 字鐘，具有正常分、秒計(jì)時(shí)，動(dòng)態(tài)顯示的功能。分析整個(gè)電路的工作原理，分別說(shuō)明各子模塊的設(shè)計(jì)原理和調(diào)試、仿真、編 程的過(guò)程。
二、實(shí)驗(yàn)任務(wù)：
用 FPGA 器件和 EDA 技術(shù)實(shí)現(xiàn)多功能數(shù)字鐘的設(shè)計(jì)
已知條件：
1、MAX+Plus 軟件
2、FPGA 實(shí)驗(yàn)開發(fā)裝置
基本功能：
1、以數(shù)字形式顯示時(shí)、分、秒的時(shí)間；
2、小時(shí)計(jì)數(shù)器為 24 進(jìn)制；
3、分、秒計(jì)數(shù)器為 60 進(jìn)制。
三、底層模塊設(shè)計(jì)（電路原理圖及仿真）
1、小時(shí)計(jì)數(shù)器為24進(jìn)制 電路原理圖
仿真圖
封裝圖
2、分、秒計(jì)時(shí)器都為60進(jìn)制 電路原理圖
仿真圖
封裝圖
四、總體方案
按照上述實(shí)驗(yàn)要求，本次電子數(shù)字時(shí)鐘實(shí)驗(yàn)，通過(guò)兩個(gè)模 60 計(jì)數(shù)器及一個(gè)模 24 計(jì)數(shù)器級(jí)聯(lián)既可以實(shí)現(xiàn)計(jì)時(shí)模塊。多功能數(shù)字鐘的主體部分 電路原理圖
仿真圖
封裝圖
五、心得體會(huì)
剛剛開始覺得做這個(gè)電子實(shí)驗(yàn)報(bào)告挺難的，因?yàn)閷?duì)軟件的不熟悉和對(duì)這個(gè)實(shí)驗(yàn)操作的也不熟悉，對(duì)著老師給的資料也做了很長(zhǎng)時(shí)間，就是仿真的時(shí)候有些該注意的沒有注意，導(dǎo)致仿真失敗，但是后來(lái)還是自己慢慢拿的請(qǐng)教同學(xué)、老師哪里出了問(wèn)題，后來(lái)才做出來(lái)了，把60進(jìn)制的做出來(lái)了，后來(lái)的24進(jìn)制按照老師給的電路原理圖也成功了仿真出來(lái)，我用了很長(zhǎng)時(shí)間才編寫出來(lái)，現(xiàn)在看看，也沒有那么難了。同時(shí)請(qǐng)教老師，和同學(xué)、通過(guò)實(shí)驗(yàn)掌握一些邏輯組合器件的基本功能和用法?？傊液芨兄x這次實(shí)驗(yàn)可以給我這樣的機(jī)會(huì)，這個(gè)實(shí)驗(yàn)給了我很對(duì)的收獲，我相信這會(huì)對(duì)我以后的學(xué)習(xí)很有幫助。
第四篇：eda 實(shí)現(xiàn)多功能數(shù)字鐘
一、標(biāo)題：EDA實(shí)現(xiàn)多功能數(shù)字鐘
二、任務(wù)書：設(shè)計(jì)要求是用FPGA器件和EDA技術(shù)實(shí)現(xiàn)多功能數(shù)字鐘的設(shè)計(jì)，⑴ 控制功能包括①以數(shù)字形式顯示時(shí)、分、秒的時(shí)間；②小時(shí)計(jì)數(shù)器為24進(jìn)制；③分、秒計(jì)數(shù)器為60進(jìn)制；④有兩個(gè)使能端起到校時(shí)、校分的作用，同時(shí)按無(wú)效；⑤每小時(shí)的59分51、53、55、57、59分別以四長(zhǎng)聲一短聲進(jìn)行模擬電臺(tái)仿真；⑥讓信號(hào)燈在晚上19點(diǎn)至早上5點(diǎn)亮；⑵ 在Max＋plusⅡ軟件系統(tǒng)平臺(tái)上建立多功能數(shù)字鐘電路的頂層電路文件并完成編譯和仿真，并對(duì)器件進(jìn)行下載檢查。
三、關(guān)鍵詞：數(shù)字鐘 原理電路 編譯 仿真 下載
四、數(shù)字鐘電路系統(tǒng)的組成框圖：
五、各功能模塊設(shè)計(jì)、仿真波形及其分析說(shuō)明：
1、小時(shí)計(jì)時(shí)模塊：
仿真波形：
分析說(shuō)明：
當(dāng)小時(shí)的高四位為0、1時(shí)，小時(shí)的低四位為九時(shí)，在下一個(gè)時(shí)鐘的上跳延來(lái)了之后，高四位加一；當(dāng)小時(shí)的高四位為2，同時(shí)低四位為3時(shí)，小時(shí)的高低四位都清零。實(shí)現(xiàn)從00到23的循環(huán)計(jì)數(shù)。
2、分鐘計(jì)時(shí)模塊：
仿真波形：
分析說(shuō)明：
當(dāng)分鐘的高四位為0、1、2、3、4時(shí)，小時(shí)的低四位為九時(shí)，在下一個(gè)時(shí)鐘的上跳延來(lái)了之后，高四位加一；當(dāng)分鐘的高四位為5時(shí)，同時(shí)低四位為9時(shí)，分鐘的高低四位都清零，實(shí)現(xiàn)從00到59的循環(huán)計(jì)數(shù)。
3、秒計(jì)時(shí)模塊（與分計(jì)時(shí)模塊相同）；
4、校時(shí)、校分模塊：
仿真波形：
分析說(shuō)明：
SWM、SWH兩開關(guān)先設(shè)置1，秒時(shí)鐘，分時(shí)鐘，小時(shí)時(shí)鐘分別設(shè)置為不同頻率的時(shí)鐘，當(dāng)開關(guān)SWM置0即按下時(shí)，秒時(shí)鐘CPS對(duì)分鐘進(jìn)行校對(duì)，即如圖所示CPM在SWM為0時(shí)頻率與CPS相同；同理，當(dāng)SWH為0時(shí)用秒時(shí)鐘對(duì)小時(shí)進(jìn)行校對(duì)，即CPH在SWH為0時(shí)頻率與CPS相同。當(dāng)SWM、SWH都不為0時(shí)，分鐘、小時(shí)正常計(jì)時(shí)。
5、整點(diǎn)報(bào)時(shí)模塊：
仿真波形：
分析說(shuō)明：
為實(shí)現(xiàn)時(shí)鐘在59分51秒53秒55秒57秒時(shí)，以低音報(bào)時(shí)，當(dāng)為59分59秒時(shí)以高音報(bào)時(shí)；所以將M[7..0]從高位到低位設(shè)置為0101 1001轉(zhuǎn)換成十進(jìn)制即為59分，秒的十位都為5所以S7到S4設(shè)置為0101，秒的個(gè)位1、3、5、7、9，即0001、0011、0101、0111、1001，從S3到S0只有當(dāng)S3設(shè)置為1的時(shí)候秒個(gè)位為9，通過(guò)分頻以1000HZ輸出以實(shí)現(xiàn)高音報(bào)時(shí)；1、3、5、7時(shí)S0都為0，為能同時(shí)確定1、3、5、7則將S0設(shè)置為0，S1、S2則為任意。如波形所示，S3取一段設(shè)置為1時(shí)，輸出FU變?yōu)?000HZ的高頻報(bào)時(shí)，其余狀態(tài)一致為500HZ低頻報(bào)時(shí)，從而實(shí)現(xiàn)預(yù)期情況。
6、時(shí)段控制模塊：
仿真波形：
分析說(shuō)明：
從19點(diǎn)到凌晨5點(diǎn)（含5點(diǎn)），燈亮，即完成時(shí)段控制。
六、頂層邏輯電路圖、仿真波形及分析結(jié)論：
建立一個(gè)頂層文件如圖：
仿真波形如下：
分析結(jié)論：
經(jīng)仿真波形分析①走時(shí)正常；②能〝校時(shí)〞〝校分〞；③整點(diǎn)報(bào)時(shí)；④時(shí)段控制到位。功能完全符合設(shè)計(jì)要求，可以下載。
七、定義芯片管腳號(hào)（列表示意）及下載過(guò)程：
1、由于提供的實(shí)驗(yàn)箱的七段顯示器是掃描形式工作，需要進(jìn)行譯碼以及選擇掃描，需添加模塊：
該模塊有三部分組成，包括一個(gè)8進(jìn)制計(jì)數(shù)器，一個(gè)3-8數(shù)據(jù)選擇器及七段顯示譯碼器：
將該模塊連入最后的頂層文件中，即可進(jìn)行下載工作。
2、按鍵掃描模塊：由于試驗(yàn)箱提供的按鍵系統(tǒng)為4*4掃描矩陣，需將橫向或縱向按鍵設(shè)置0或1，該模塊只需要在頂層文件中接4個(gè)output出來(lái)接地，如圖：
3、分配輸入、輸出信號(hào)在器件上的引腳號(hào)：
4、引腳分配表：
5、對(duì)器件進(jìn)行下載：
選MAX+plus II/Programmer，彈出編程對(duì)話框，如圖：
檢查編程文件名和器件，正確，接上硬件后，點(diǎn)擊器件編程。即完成下載。
八、課程設(shè)計(jì)中遇到問(wèn)題及解決方法
Q1：下載后，秒鐘不進(jìn)位
A：檢查原理電路發(fā)現(xiàn)輸入輸出接錯(cuò)位，經(jīng)更正正常； Q2：到59分51秒等不鬧鐘
A：檢查蜂鳴器是否接錯(cuò)管腳，下載器上套線是否接好，最后發(fā)現(xiàn)是套線的問(wèn)題，解決后，正常鳴叫。
九、課程設(shè)計(jì)項(xiàng)目最終結(jié)論
通過(guò)各模塊級(jí)聯(lián)最后成功下載，實(shí)現(xiàn)了兩個(gè)使能對(duì)分秒校時(shí)，整點(diǎn)仿電臺(tái)報(bào)時(shí)以及時(shí)段控制的多功能數(shù)字鐘。
十、心得體會(huì)：
實(shí)驗(yàn)過(guò)程中最然遇到了很多困難，從畫圖到理解電路圖，還有接觸沒有接觸過(guò)的下載，把紙上的東西用到了硬件中，質(zhì)的改變?？吹匠晒Φ臄?shù)字鐘，很有成就感。好像聽到的蜂鳴聲是從未聽到過(guò)的美妙樂(lè)曲。課設(shè)給我們指引了又一工作方向，培養(yǎng)對(duì)這些的興趣，對(duì)以后工作應(yīng)該很有幫助，所以堅(jiān)定了我課后還要多看書多學(xué)習(xí)這方面知識(shí)的信念。
十一、參閱教材及文獻(xiàn)：
《電子線路實(shí)驗(yàn)設(shè)計(jì)仿真講義》
按鈕，直接對(duì)
第五篇：多功能數(shù)字鐘課程設(shè)計(jì)VHDL代碼書上程序改
library ieee;use ieee.std_logic_1164.all;entity clock is port(clk1hz:in std_logic;--1hz脈沖--clk100:in std_logic;--100hz脈沖--weekclk:in std_logic;--星期調(diào)整脈沖--start_stop:in std_logic;--秒表啟動(dòng)/停止控制--reset:in std_logic;--秒表復(fù)位--adclk:in std_logic;--校時(shí)脈沖--setselect:in std_logic;--調(diào)整位選擇脈沖--mode:in std_logic;--功能選擇脈沖--showdate:in std_logic;--日期顯示--dis:out std_logic_vector(23 downto 0);--顯示輸出--glisten:out std_logic_vector(5 downto 0);--閃爍指示--weekout:out std_logic_vector(3 downto 0);--星期輸出--qh:out std_logic--整點(diǎn)報(bào)時(shí)--);end clock;architecture arch of clock is component adjust
port（adclk: in std_logic;
data_in: out std_logic_vector(7 downto 0));end component;component control
port（setclk: in std_logic;
setlap: out std_logic_vector(1 downto 0);
mode: in std_logic;
module: out std_logic_vector(2 downto 0));end component;component weekcounter
port（clk: in std_logic;
clk2: in std_logic;
q: out std_logic_vector(3 downto 0));end component;component stopwatch
port（clk: in std_logic;
reset: in std_logic;
start_stop: in std_logic;
centsec: out std_logic_vector(7 downto 0);
sec: out std_logic_vector(7 downto 0);
min: out std_logic_vector(7 downto 0));end component;component h_m_s_count
port（clk: in std_logic;
set: in std_logic;
setlap: in std_logic_vector(1 downto 0);
d:in std_logic_vector(7 downto 0);
sec:out std_logic_vector(7 downto 0);
min:out std_logic_vector(7 downto 0);
hour:out std_logic_vector(7 downto 0);
qh:out std_logic;
qc: out std_logic);end component;component y_m_d_count
port（clk: in std_logic;
set: in std_logic;
setlap: in std_logic_vector(1 downto 0);
data_in: in std_logic_vector(7 downto 0);
day: out std_logic_vector(7 downto 0);
month: out std_logic_vector(7 downto 0);
year: out std_logic_vector(7 downto 0));end component;component display
port（module: in std_logic_vector(2 downto 0);
showdate:in std_logic;
clk:in std_logic;
setlap:in std_logic_vector(1 downto 0);
watch: in std_logic_vector(23 downto 0);
time:in std_logic_vector(23 downto 0);
date:in std_logic_vector(23 downto 0);
dis: out std_logic_vector(23 downto 0);
glisten:out std_logic_vector(5 downto 0));end component;signal data_in,mcentsec,msec,mmin,ssec,smin,shour,sdate,smonth,syear:std_logic_vector(7 downto 0);signal setlap:std_logic_vector(1 downto 0);signal module:std_logic_vector(2 downto 0);signal qc:std_logic;signal watch,time,date:std_logic_vector(23 downto 0);begin u1:adjust port map(adclk,data_in);u2:control port map(setselect,setlap,mode,module);u3:stopwatch port map(clk100,reset,start_stop,mcentsec,msec,mmin);u4:h_m_s_count port map(clk1hz,module(1),setlap,data_in,ssec,smin,shour,qh,qc);u5:y_m_d_count port map(qc,module(2),setlap,data_in,sdate,smonth,syear);u6:display port map(module,showdate,clk1hz,setlap,watch,time,date,dis,glisten);u7:weekcounter port map(qc,weekclk,weekout);watch<=mmin&msec&mcentsec;time<=shour&smin&ssec;date<=syear&smonth&sdate;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity adjust is
port（adclk: in std_logic;
data_in: out std_logic_vector(7 downto 0));end adjust;architecture arch of adjust is signal temp2,temp1:std_logic_vector(3 downto 0);begin process(adclk)begin if rising_edge(adclk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;end if;end if;data_in<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity control is
port（setclk: in std_logic;--調(diào)整脈沖--
setlap: out std_logic_vector(1 downto 0);--調(diào)整位選擇脈沖--
mode: in std_logic;--功能選擇脈沖--
module: out std_logic_vector(2 downto 0)--功能輸出--);end control;architecture arch of control is signal ssetlap:std_logic_vector(1 downto 0);signal s:std_logic_vector(3 downto 0);begin process(mode,setclk)begin if mode='1'then ssetlap<=“00”;elsif rising_edge(setclk)then if ssetlap=“10”then ssetlap<=“00”;else ssetlap<=ssetlap+'1';end if;end if;end process;setlap<=ssetlap;process(mode)begin if rising_edge(mode)then case s is when“0001”=>s<=“0010”;when“0010”=>s<=“0100”;when“0100”=>s<=“1000”;when“1000”=>s<=“0001”;when others=>s<=“0010”;end case;end if;end process;module<=s(3 downto 1);end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter60 is
port（clk: in std_logic;--計(jì)數(shù)脈沖--
clr: in std_logic;--復(fù)位--
q: out std_logic_vector(7 downto 0);--計(jì)數(shù)值--
qc:out std_logic--進(jìn)位輸出--);end counter60;architecture arch of counter60 is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clr,clk)begin if clr='1'then temp1<=“0000”;temp2<=“0000”;elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else temp1<=temp1+'1';end if;if temp2=“0101” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter99 is
port（clk: in std_logic;--100vhz計(jì)數(shù)脈沖--
en: in std_logic;--計(jì)數(shù)使能--
clr: in std_logic;--復(fù)位--
q: out std_logic_vector(7 downto 0);--計(jì)數(shù)值--
qc: out std_logic--進(jìn)位--);end counter99;
architecture arch of counter99 is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clr,clk)begin if clr='1'then temp1<=“0000”;temp2<=“0000”;elsif rising_edge(clk)then if en='1' then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity daycounter is
port（clk: in std_logic;--計(jì)數(shù)脈沖--
set: in std_logic;--調(diào)整信號(hào)--
day_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--
day_out: out std_logic_vector(7 downto 0);--天輸出--
qc: out std_logic;--進(jìn)位--
day28: in std_logic;--該位為1表示該月為28天--
day29: in std_logic;--該位為1表示該月為29天--
day30: in std_logic;--該位為1表示該月為30天--
day31: in std_logic--該位為1表示該月為31天--);end daycounter;architecture arch of daycounter is signal temp1,temp2:std_logic_vector(3 downto 0);signal days:std_logic_vector(7 downto 0);begin days<=“00101000” when day28='1'else
“00101001”when day29='1'else
“00110000”when day30='1'else
“00110001”when day31='1'else
“00000000”;process(clk,set,day_in,days)begin if set='1' then temp2<=day_in(7 downto 4);temp1<=day_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else temp1<=temp1+'1';end if;if temp2&temp1=days then temp2<=“0000”;temp1<=“0001”;qc<='1';else qc<='0';end if;end if;end process;day_out<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity days_control is port（month: in std_logic_vector(7 downto 0);--月份--
year2: in std_logic;--年份高位數(shù)字bcd碼最低位--
year1: in std_logic_vector(1 downto 0);--年份低位數(shù)字bcd碼末兩位--
day28: out std_logic;--該位為1表示該月為28天--day29: out std_logic;--該位為1表示該月為29天--
day30: out std_logic;--該位為1表示該月為30天--
day31: out std_logic--該位為1表示該月為31天--);end days_control;architecture arch of days_control is begin process(month,year2,year1)begin case month is when “00000001”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000010”=>if(year2='0'and year1=“00”)or(year2='1'and year1=“10”)then
day28<='0';day29<='1';day30<='0';day31<='0';
else
day28<='1';day29<='0';day30<='0';day31<='0';
end if;when “00000011”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000100”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00000101”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00000110”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00000111”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00001000”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00001001”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00010000”=>day28<='0';day29<='0';day30<='0';day31<='1';when “00010001”=>day28<='0';day29<='0';day30<='1';day31<='0';when “00010010”=>day28<='0';day29<='0';day30<='0';day31<='1';when others=>day28<='0';day29<='0';day30<='0';day31<='1';end case;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity display is
port（module: in std_logic_vector(2 downto 0);--功能選擇--
showdate:in std_logic;--顯示日期--
clk:in std_logic;--閃爍脈沖--
setlap:in std_logic_vector(1 downto 0);--閃爍位選擇--
watch: in std_logic_vector(23 downto 0);--秒表計(jì)數(shù)值輸入--
time:in std_logic_vector(23 downto 0);--時(shí)分秒計(jì)數(shù)值輸入--date:in std_logic_vector(23 downto 0);--年月日計(jì)數(shù)值輸入--
dis: out std_logic_vector(23 downto 0);--顯示輸出--
glisten:out std_logic_vector(5 downto 0)--閃爍輸出--);end display;architecture arch of display is begin process(module,showdate,watch,time,date)begin if showdate='1'then dis<=date;else case module is when“001”=>dis<=watch;when“010”=>dis<=time;when“100”=>dis<=date;when others=>dis<=time;end case;end if;end process;process(clk,module,setlap)begin if module=“010”or module=“100”then case setlap is when“00”=>glisten(1 downto 0)<=clk&clk;
glisten(5 downto 2)<=“0000”;when“01”=>glisten(3 downto 2)<=clk&clk;
glisten(5 downto 4)<=“00”;
glisten(1 downto 0)<=“00”;when“10”=>glisten(5 downto 4)<=clk&clk;
glisten(3 downto 0)<=“0000”;when others=>glisten<=“000000”;end case;else glisten<=“000000”;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity dmux is
port（set:in std_logic;--調(diào)整信號(hào)--
setlap: in std_logic_vector(1 downto 0);--調(diào)整位選擇--
d: in std_logic_vector(7 downto 0);--調(diào)整輸入--
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end dmux;architecture arch of dmux is begin process(set,setlap,d)begin if set='1' then case setlap is when“00”=>set1<='1';set2<='0';set3<='0';
q1<=d;when“01”=>set1<='0';set2<='1';set3<='0';
q2<=d;when“10”=>set1<='0';set2<='0';set3<='1';
q3<=d;when others=>set1<='0';set2<='0';set3<='0';end case;else set1<='0';set2<='0';set3<='0';end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity h_m_s_count is
port（clk: in std_logic;--1hz脈沖--
set: in std_logic;--調(diào)整信號(hào)--
setlap: in std_logic_vector(1 downto 0);--調(diào)整位選擇--
d:in std_logic_vector(7 downto 0);--調(diào)整輸入--
sec:out std_logic_vector(7 downto 0);--秒輸出--
min:out std_logic_vector(7 downto 0);--分輸出--
hour:out std_logic_vector(7 downto 0);--小時(shí)輸出--
qh:out std_logic;--整點(diǎn)報(bào)時(shí)--
qc: out std_logic--進(jìn)位--);end h_m_s_count;architecture arch of h_m_s_count is component sec_mincounter
port（clk: in std_logic;
set:in std_logic;
d:in std_logic_vector(7 downto 0);
q:out std_logic_vector(7 downto 0);
qc:out std_logic);end component;component hourcounter port（clk: in std_logic;
set:in std_logic;
d:in std_logic_vector(7 downto 0);
q: out std_logic_vector(7 downto 0);
qc:out std_logic);end component;component dmux
port（set:in std_logic;
setlap: in std_logic_vector(1 downto 0);
d: in std_logic_vector(7 downto 0);
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end component;signal secset,minset,hourset: std_logic;signal secin,minin,hourin:std_logic_vector(7 downto 0);signal qcsec,qcmin,qchour: std_logic;begin u1:dmux port map(set,setlap,d,secset,minset,hourset,secin,minin,hourin);u2:sec_mincounter port map(clk,secset,secin,sec,qcsec);u3:sec_mincounter port map(qcsec,minset,minin,min,qcmin);u4:hourcounter port map(qcmin,hourset,hourin,hour,qchour);qh<=qcmin;qc<=qchour;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity hourcounter is
port（clk: in std_logic;--計(jì)數(shù)脈沖--
set:in std_logic;--調(diào)整信號(hào)--
d:in std_logic_vector(7 downto 0);--調(diào)整時(shí)間--
q: out std_logic_vector(7 downto 0);--小時(shí)輸出--
qc:out std_logic--進(jìn)位--);end hourcounter;architecture arch of hourcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set)begin if set='1'then temp2<=d(7 downto 4);temp1<=d(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0010” and temp1=“0100” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end process;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity monthcounter is
port（clk: in std_logic;--計(jì)數(shù)脈沖--
set: in std_logic;--調(diào)整信號(hào)--
month_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--
month_out: out std_logic_vector(7 downto 0);--月輸出--
qc: out std_logic--進(jìn)位--);end monthcounter;architecture arch of monthcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set,month_in)begin if set='1' then temp2<=month_in(7 downto 4);temp1<=month_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0001”and temp1=“0010” then temp2<=“0000”;temp1<=“0001”;qc<='1';else qc<='0';end if;end if;end process;month_out<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity sec_mincounter is port（clk: in std_logic;--計(jì)數(shù)脈沖--
set:in std_logic;--調(diào)整信號(hào)--
d:in std_logic_vector(7 downto 0);--調(diào)整時(shí)間輸入--
q:out std_logic_vector(7 downto 0);--分和秒輸出--
qc:out std_logic--進(jìn)位--);end sec_mincounter;architecture arch of sec_mincounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set)begin if set='1'then temp2<=d(7 downto 4);temp1<=d(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“0101” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;qc<='1';else qc<='0';end if;end if;end process;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity stopwatch is port（clk: in std_logic;--100hz脈沖--
reset: in std_logic;--復(fù)位--
start_stop: in std_logic;--啟動(dòng)/停止--
centsec: out std_logic_vector(7 downto 0);--百分秒輸出，當(dāng)超過(guò)60分轉(zhuǎn)為秒--
sec: out std_logic_vector(7 downto 0);--秒輸出，當(dāng)超過(guò)60分轉(zhuǎn)為分--
min: out std_logic_vector(7 downto 0)--分輸出，當(dāng)超過(guò)60分轉(zhuǎn)為小時(shí)--);end stopwatch;architecture arch of stopwatch is component counter99 port（clk: in std_logic;
en: in std_logic;
clr: in std_logic;
q: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;component counter60 port（clk: in std_logic;
clr: in std_logic;
q: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;signal qc1,qc2,qc3,qc4,flag:std_logic;signal tcentsec,tsec,tmin,thour:std_logic_vector(7 downto 0);begin u1:counter99 port map(clk,start_stop,reset,tcentsec,qc1);u2:counter60 port map(qc1,reset,tsec,qc2);u3:counter60 port map(qc2,reset,tmin,qc3);u4:counter60 port map(qc3,reset,thour,qc4);process(qc3)begin if rising_edge(qc3)then flag<='1';end if;if flag='1' then centsec<=tsec;sec<=tmin;min<=thour;else centsec<=tcentsec;sec<=tsec;min<=tmin;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity weekcounter is
port（clk: in std_logic;--天脈沖--
clk2: in std_logic;--外部星期調(diào)整脈沖--
q: out std_logic_vector(3 downto 0)--星期輸出--);end weekcounter;architecture arch of weekcounter is signal temp:std_logic_vector(3 downto 0);signal cp:std_logic;begin cp<=clk or clk2;process begin wait until rising_edge(cp);if temp=“0111” then temp<=“0001”;else
temp<=temp+'1';end if;q<=temp;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity y_m_d_count is
port（clk: in std_logic;--計(jì)數(shù)脈沖--
set: in std_logic;--調(diào)整信號(hào)--
setlap: in std_logic_vector(1 downto 0);--調(diào)整位選擇--
data_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--
day: out std_logic_vector(7 downto 0);--日輸出--
month: out std_logic_vector(7 downto 0);--月輸出--
year: out std_logic_vector(7 downto 0)--年輸出--);end y_m_d_count;architecture arch of y_m_d_count is component daycounter
port（clk: in std_logic;
set: in std_logic;
day_in: in std_logic_vector(7 downto 0);
day_out: out std_logic_vector(7 downto 0);
qc: out std_logic;
day28: in std_logic;
day29: in std_logic;
day30: in std_logic;
day31: in std_logic);end component;component monthcounter
port（clk: in std_logic;
set: in std_logic;
month_in: in std_logic_vector(7 downto 0);
month_out: out std_logic_vector(7 downto 0);
qc: out std_logic);end component;component yearcounter
port（clk: in std_logic;
set: in std_logic;
year_in: in std_logic_vector(7 downto 0);
year_out: out std_logic_vector(7 downto 0));end component;component dmux
port（set:in std_logic;
setlap: in std_logic_vector(1 downto 0);
d: in std_logic_vector(7 downto 0);
set1:out std_logic;
set2:out std_logic;
set3:out std_logic;
q1: out std_logic_vector(7 downto 0);
q2: out std_logic_vector(7 downto 0);
q3: out std_logic_vector(7 downto 0));end component;component days_control
port（month: in std_logic_vector(7 downto 0);
year2: in std_logic;
year1: in std_logic_vector(1 downto 0);
day28: out std_logic;
day29: out std_logic;
day30: out std_logic;
day31: out std_logic);end component;signal dayset,monthset,yearset: std_logic;signal qcday,qcmonth: std_logic;signal dayin,monthin,yearin: std_logic_vector(7 downto 0);signal smonth,syear:std_logic_vector(7 downto 0);signal day28,day29,day30,day31:std_logic;begin u1:dmux port map(set,setlap,data_in,dayset,monthset,yearset,dayin,monthin,yearin);u2:daycounter port map(clk,dayset,dayin,day,qcday,day28,day29,day30,day31);u3:monthcounter port map(qcday,monthset,monthin,smonth,qcmonth);u4:yearcounter port map(qcmonth,yearset,yearin,syear);u8:days_control port map(smonth,syear(4),syear(1 downto 0),day28,day29,day30,day31);month<=smonth;year<=syear;
end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yearcounter is
port（clk: in std_logic;--計(jì)數(shù)脈沖--
set: in std_logic;--調(diào)整信號(hào)--
year_in: in std_logic_vector(7 downto 0);--調(diào)整輸入--
year_out: out std_logic_vector(7 downto 0)--年輸出--);end yearcounter;architecture arch of yearcounter is signal temp1,temp2:std_logic_vector(3 downto 0);begin process(clk,set,year_in)begin if set='1' then temp2<=year_in(7 downto 4);temp1<=year_in(3 downto 0);elsif rising_edge(clk)then if temp1=“1001” then temp2<=temp2+'1';temp1<=“0000”;else
temp1<=temp1+'1';end if;if temp2=“1001” and temp1=“1001” then temp1<=“0000”;temp2<=“0000”;end if;end if;end process;year_out<=temp2&temp1;end arch;
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