第一篇：廣播電臺(tái)整點(diǎn)報(bào)時(shí)
周一至周五整點(diǎn)報(bào)時(shí)
06：00一日之計(jì)在于晨，一天中的美好時(shí)光從早上開(kāi)始。
07：00早上七點(diǎn)，新的一天找到新的動(dòng)力。
07：00匆忙的早晨一袋牛奶、一只雞蛋加上幾片面包它就能為您提供一上午的能量?，F(xiàn)在是早上7點(diǎn)。08：00在工作和學(xué)習(xí)開(kāi)始之前，喝杯水，它能促進(jìn)代謝，幫助醒腦。現(xiàn)在是早上8點(diǎn)。
09：00繁忙而緊張的工作需要理清頭緒，今天你做到了嗎？現(xiàn)在是北京時(shí)間9點(diǎn)整
10：00工作中帶著微笑，讓微笑感染周?chē)娜恕，F(xiàn)在是北京時(shí)間上午10點(diǎn)整。
11：00忙了一上午，抽個(gè)空，遠(yuǎn)眺下遠(yuǎn)方的綠色讓眼睛得到適當(dāng)?shù)男菹ⅲF(xiàn)在是上午十一點(diǎn)。12：00又是一個(gè)交通小高峰，回家路上注意安全！現(xiàn)在是北京時(shí)間中午12點(diǎn)整。
13：00午休小憩一會(huì)兒，下午的工作將事半功倍?，F(xiàn)在是北京時(shí)間下午1點(diǎn)整。
14：00喝杯濃茶，振作精神，下午兩點(diǎn)，有音樂(lè)的陪伴讓工作更順暢。
15：00事都有著多面性，換個(gè)方向，或許你能發(fā)現(xiàn)更多答案?，F(xiàn)在是下午三點(diǎn)。
16：00在忙碌中找尋休憩，在平淡中找尋快樂(lè)。多一些快樂(lè)，少一絲束縛?，F(xiàn)在是下午四點(diǎn) 17：00關(guān)愛(ài)他人，從小事開(kāi)始。現(xiàn)在是北京時(shí)間下午5點(diǎn)整。
18：00下班高峰期，注意行車(chē)安全?，F(xiàn)在是北京時(shí)間旁晚6點(diǎn)。
19：00關(guān)注時(shí)事動(dòng)態(tài)，了解新聞大事，新聞聯(lián)播更精彩。
20：00在城市的夜空下，欣賞喧囂的夜晚，現(xiàn)在是晚上八點(diǎn)。
21：00讓時(shí)間承載記憶，讓歲月留下印記?，F(xiàn)在是北京時(shí)間晚上9點(diǎn)整。
22：00喝一杯牛奶，融化一天的疲倦?，F(xiàn)在是北京時(shí)間晚上10點(diǎn)整。
23：00寂靜的深夜，依舊有好聲音陪伴。現(xiàn)在是北京時(shí)間晚上11點(diǎn)整。
24：00靜謐的午夜，道一聲：“晚安"?，F(xiàn)在是晚上12點(diǎn)。
工作張弛有度，生活追求品質(zhì)，
第二篇：多功能數(shù)字鐘課程設(shè)計(jì)整點(diǎn)報(bào)時(shí)與鬧鐘功能VHDL代碼
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity timkeeper is
Port(up,setpin,upclk,settime,run : in std_logic;
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0);
result: out std_logic);end timkeeper;
architecture Behavioral of timkeeper is
component h_m_s_time port（clk0,clk1,ce : in std_logic;
sec0,sec1 : buffer std_logic_vector(3 downto 0);
lock : in std_logic_vector(2 downto 0);
up : in std_logic;min0,min1 : buffer std_logic_vector(3 downto 0);hour0,hour1 : buffer std_logic_vector(3 downto 0);ov : out std_logic);end component;component date port（clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
date0,date1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);
end component;component month_year port（clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1 : buffer std_logic_vector(3 downto 0);
year0,year1 : buffer std_logic_vector(3 downto 0));end component;component LED_disp port（lock : in std_logic_vector(2 downto 0);
sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);
date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0));end component;component alarm Port（hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
settime,run : in std_logic;
result : out std_logic);end component;
signal Tlock:std_logic_vector(2 downto 0);signal Tsecond_wave:std_logic;signal Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1:std_logic_vector(3 downto 0);signal Tdate0,Tdate1,Tmon0,Tmon1,Tyear0,Tyear1:std_logic_vector(3 downto 0);signal Tovday,Tovmonth:std_logic;signal vcc:std_logic;begin vcc<='1';process(setpin)begin
if rising_edge(setpin)then
Tlock<=Tlock+'1';
end if;
end process;
u2:h_m_s_time port map(Tsecond_wave,upclk,vcc,Tsec0,Tsec1,Tlock,up，Tmin0,Tmin1,Thour0,Thour1,Tovday);u3:date port map(Tovday,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1，Tdate0,Tdate1,Tovmonth);u4:month_year port map(Tovmonth,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1);u5:LED_disp port map(Tlock,Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,Tdate0，Tdate1,Tmon0,Tmon1,Tyear0,Tyear1,a0,a1,b0,b1,c0,c1);u6:alarm port map(Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,settime,run ,result);end Behavioral;
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity alarm is
Port(hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
settime,run : in std_logic;
result : out std_logic);end alarm;
architecture Behavioral of alarm is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);begin p0:process(settime)
begin
if settime='1'then
dhour1<=hour1;
dhour0<=hour0;
dmin1<=min1;
dmin0<=min0;
dsec1<=sec1;
dsec0<=sec0;
end if;
end process p0;p1:process(run)
begin if run='1'then
if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then
result<='1';
else result<='0';
end if;else result<='0';end if;
end process p1;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity date is
Port(clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
date0,date1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);end date;
architecture Behavioral of date is signal tempy0:std_logic_vector(1 downto 0);signal tempy1,clk:std_logic;signal Td0,Td1:std_logic_vector(3 downto 0);begin tempy0<=year0(1 downto 0);tempy1<=year1(0);Td0<=date0;Td1<=date1;u1:process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then clk<=clk0;
else clk<=clk1;
end if;
end process u1;
u2:process(clk,ce)
begin
if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“100” and up='1')then
if(mon0=“0010” and mon1=“0000”)then
Feb_add_day(Td0,Td1,tempy0,tempy1,date0,date1);
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and or(mon0=“0101” and mon1=“0000”)or(mon0=“0111” and mon1=“0000”)
mon1=“0000”)
or(mon0=“1000” and mon1=“0000”)or(mon0=“0000”and mon1=“0001”)or(mon0=“0010” and mon1=“0001”))then
oddmonth_add_day(Td0,Td1,date0,date1);
else evenmonth_add_day(Td0,Td1,date0,date1);
end if;
end if;
if(lock=“100” and up='0')then
if(mon0=“0010” and mon1=“0000”)then
Feb_sub_day(Td0,Td1,tempy0,tempy1,date0,date1);
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0101” and mon1=“0000”)or
(mon0=“0111” and mon1=“0000”)or(mon0=“1000” and mon1=“0000”)or(mon0=“0000” and mon1=“0001”)or(mon0=“0010”
and mon1=“0001”))then
oddmonth_sub_day(Td0,Td1,date0,date1);
else evenmonth_sub_day(Td0,Td1,date0,date1);
end if;
end if;
end if;
end if;
end process u2;
u3:process(ce)
begin
if rising_edge(clk)then
if(lock/=“000” and lock/=“001”)then
ov<='0';
elsif(ce='1')then
if(mon0=“0010” and mon1=“0000”)then
if((tempy1='0' and tempy0=“00”)or(tempy1='1' and tempy0=“10”))then
if(date0=“1001” and date1=“0010”)then
ov<='1';
else ov<='0';
end if;
elsif(date0=“1000” and date1=“0010”)then ov<='1';else ov<='0';end if;
elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0010” and mon1=“0000”)
or(mon0=“0111” and mon1=“0000”)or(mon0=“1000” or(mon0=“0000” and mon1=“0001”)
or(mon0=“0010” and mon1=“0001”))then
if(date0=“0001” and date1=“0011”)then
ov<='1';
else ov<='0';
end if;
elsif(date0=“0000” and date1=“0011”)then
ov<='1';
else ov<='0';
end if;
end if;
end if;
end process u3;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;
and
mon1=“0000”)use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity h_m_s_time is
Port(clk0,clk1,ce : in std_logic;
sec0,sec1 : buffer std_logic_vector(3 downto 0);
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
min0,min1 : buffer std_logic_vector(3 downto 0);
hour0,hour1 : buffer std_logic_vector(3 downto 0);
ov : out std_logic);end h_m_s_time;
architecture Behavioral of h_m_s_time is signal Ts0,Ts1,Tm0,Tm1,Th0,Th1:std_logic_vector(3 downto 0);signal clk:std_logic;begin
Ts0<=sec0;Ts1<=sec1;Tm0<=min0;Tm1<=min1;Th0<=hour0;Th1<=hour1;u1: process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then
clk<=clk0;
else clk<=clk1;
end if;
end process u1;
u2: process(clk,lock)
begin
if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“111” and up='1')then
addsec_addmin(Ts0,Ts1,sec0,sec1);
end if;
if(lock=“111” and up='0')then
subsec_submin(Ts0,Ts1,sec0,sec1);
end if;
if(lock=“000” or lock=“001”)then
if(sec0=“1001” and sec1=“0101”)then
addsec_addmin(Tm0,Tm1,min0,min1);
end if;
if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”)then
addhour(Th0,Th1,hour0,hour1);
end if;
if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”
and hour0=“0011” and hour1=“0010”)then
ov<='1';
else ov<='0';
end if;
end if;
if(lock=“110” and up='1')then
addsec_addmin(Tm0,Tm1,min0,min1);
end if;
if(lock=“101” and up='0')then
subsec_submin(Tm0,Tm1,min0,min1);
end if;
if(lock=“101” and up='1')then
addhour(Th0,Th1,hour0,hour1);
end if;
if(lock=“101” and up='0')then
subhour(Th0,Th1,hour0,hour1);
end if;
end if;
end if;
end process u2;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity LED_disp is
Port(lock : in std_logic_vector(2 downto 0);
sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);
date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);
a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0));end LED_disp;
architecture Behavioral of LED_disp is begin process(lock,sec0,sec1,min0,min1,hour0,hour1,date0,date1,mon0,mon1,year0,year1)
begin
if(lock=“000”)then
a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;
end if;
if(lock=“000”)then
a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;
end if;
if(lock=“001”)then
a0<=date0;a1<=date1;b0<=mon0;b1<=mon1;c0<=year0;c1<=year1;
end if;
if(lock=“101”)then
a0<=“0000”;a1<=“0000”;b0<=“0000”;b1<=“0000”;c0<=hour0;c1<=hour1;
end if;
if(lock=“110”)then
a0<=“0000”;a1<=“0000”;b0<=min0;b1<=min1;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“111”)then
a0<=sec0;a1<=sec1;b0<=“0000”;b1<=“0000”;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“010”)then a0<=“0000”;a1<=“0000”;b0<=“0000”;b1<=“0000”;c0<=year0;c1<=year1;end if;if(lock=“011”)then
a0<=“0000”;a1<=“0000”;b0<=mon0;b1<=mon1;c0<=“0000”;c1<=“0000”;
end if;
if(lock=“100”)then
a0<=date0;a1<=date1;b0<=“0000”;b1<=“0000”;c0<=“0000”;c1<=“0000”;
end if;
end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;use work.pac.all;entity month_year is
Port(clk0,clk1,ce : in std_logic;
lock : in std_logic_vector(2 downto 0);
up : in std_logic;
mon0,mon1 : buffer std_logic_vector(3 downto 0);
year0,year1 : buffer std_logic_vector(3 downto 0));end month_year;
architecture Behavioral of month_year is signal Ty0,Ty1,Tm0,Tm1:std_logic_vector(3 downto 0);signal clk:std_logic;begin
Ty0<=year0;Ty1<=year1;Tm0<=mon0;Tm1<=mon1;u1: process(lock,clk0,clk1)
begin
if(lock=“000” or lock=“001”)then
clk<=clk0;
else clk<=clk1;
end if;
end process u1;u2:process(clk,ce)begin if rising_edge(clk)then
if(ce='1')then
if(lock=“000”)or(lock=“001”)or(lock=“011” and up='1')then
add_month(Tm0,Tm1,mon0,mon1);
end if;
if(lock=“011” and up='0')then
sub_month(Tm0,Tm1,mon0,mon1);
end if;
if(lock=“000” or lock=“001”)then
if(mon0=“0010” and mon1=“0001”)then
add_year(Ty0,Ty1,year0,year1);
end if;
end if;
if(lock=“010” and up='1')then
add_year(Ty0,Ty1,year0,year1);
end if;
if(lock=“010” and up='0')then
sub_year(Ty0,Ty1,year0,year1);
end if;
end if;
end if;
end process u2;
end Behavioral;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
package pac is
procedure add_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector);procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector);procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector);procedure sub_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector);procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;
ty0:in std_logic_vector(1 downto 0);
ty1:in std_logic;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;
ty0:in std_logic_vector(1 downto 0);
ty1:in std_logic;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector);procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector);procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector);procedure addhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector);procedure subhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector);end pac;package body pac IS procedure add_year(oldyear0,oldyear1:in std_logic_vector;
signal newyear0:out std_logic_vector;
signal newyear1:out std_logic_vector)is
begin
if(oldyear0=“1001” and oldyear1/=“1001”)then
newyear0<=“0000”;newyear1<=oldyear1+'1';
else newyear0<=oldyear0+'1';
end if;if oldyear0=“1001” and oldyear1=“1001” then newyear0<=“0000”;
newyear1<=“0000”;end if;end add_year;
procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;
signal newmonth1:out std_logic_vector)is
begin
if oldmonth0=“0010” and oldmonth1=“0001” then newmonth0<=“0001”;
newmonth1<=“0000”;
elsif oldmonth0=“1001” then newmonth0<=“0000”;
newmonth1<=oldmonth1+'1';else
newmonth0<=oldmonth0+'1';end if;end add_month;procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;
signal newmonth0:out std_logic_vector;signal newmonth1: out std_logic_vector)is begin
if oldmonth0=“0001”and oldmonth1=“0000”then
newmonth0<=“0010”;newmonth1<=“0001”;
elsif oldmonth0=“0000” and oldmonth1=“0001” then
newmonth0<=“1001”;newmonth1<= oldmonth1-'1';else newmonth0<=oldmonth0-'1';end if;if oldmonth0=“0000” and oldmonth1=“0000”then
newmonth0<=“0010”;newmonth1<=“0001”;
end if;
end sub_month;procedure sub_year(oldyear0,oldyear1:in std_logic_vector;signal newyear0: out std_logic_vector;signal newyear1: out std_logic_vector)is
begin if oldyear0=“0000”then
if oldyear1=“0000”then
newyear1<=“1001”;else newyear1<= oldyear1-'1';end if;newyear0<=“1001”;else newyear0<=oldyear0-'1';end if;end sub_year;procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;
Ty0:in std_logic_vector(1 downto 0);
Ty1:in std_logic;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if oldday0=“1000”and oldday1=“0010”then
if((Ty1='0' and Ty0=“00”)or(ty1='1' and ty0=“10”))then
newday0<=oldday0 +'1';else newday0<=“0001”;newday1<=“0000”;end if;elsif oldday0=“1001” and oldday1=“0010”then
newday0<=“0001”;newday1<=“0000”;elsif oldday0=“1001” then
newday0<=“0000”;newday1<=oldday1+'1';else newday0<=oldday0+'1';end if;end Feb_add_day;
procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;
Ty0:in std_logic_vector(1 downto 0);
Ty1:in std_logic;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0000” or oldday0=“0001”)and oldday1=“0000”then
if((Ty1='0' and Ty0=“00”)or(ty1='1' and ty0=“10”))then
newday0<=“1001”;newday1<=“0010”;
else newday0<=“1000”;newday1<=“0010”;
end if;
elsif oldday0=“0000” and oldday1/=“0000”then
newday0<=“1001”;newday1<=oldday1-'1';else newday0<=oldday0-'1';end if;end Feb_sub_day;procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0001” and oldday1=“0011”)then
newday0<=“0001”;newday1<=“0000”;
elsif oldday0=“1001”then
newday0<=“0000”;newday1<=oldday1+'1';
else newday0<= oldday0+'1';
end if;
end oddmonth_add_day;procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if(oldday0=“0001” or oldday0=“0000”)and oldday1=“0000” then
newday0<=“0001”;newday1<=“0011”;
elsif oldday0=“0000” and oldday1/=“0000” then
newday0<=“1001”;newday1<=oldday1-'1';
else newday0<= oldday0-'1';
end if;
end oddmonth_sub_day;procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;
signal newday0: out std_logic_vector;
signal newday1: out std_logic_vector)is
begin
if oldday0=“0000” and oldday1=“0011” then newday0<=“0001”;
newday1<=“0000”;
elsif oldday0=“1001”then
newday0<=“0000”;
newday1<=oldday1+'1';
else newday0<=oldday0+'1';
end if;
end evenmonth_add_day;procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;
signal newday0:out std_logic_vector;
signal newday1:out std_logic_vector)is begin
if(oldday0=“0000” or oldday0=“0001”)and oldday1=“0000”then
newday0<=“0000”;
newday1<=“0011”;elsif oldday0=“0000” and oldday1/=“0000”
then newday0<=“1001”;
newday1<=oldday1-'1';else
newday0<=oldday0-'1';
end if;end
evenmonth_sub_day;
procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector)is
begin
if
(oldtime0=“1001”)then
newtime0<=“0000”;
if(oldtime1=“0101”)then
newtime1<=“0000”;
else newtime1<=oldtime1+'1';
end if;
else newtime0<=oldtime0+'1';
end if;
end addsec_addmin;procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;
signal newtime0:out std_logic_vector;
signal newtime1:out std_logic_vector)is begin
if(oldtime0=“0000”)then
newtime0<=“1001”;
if(oldtime1=“0000”)then
newtime1<=“0101”;
else newtime1<=oldtime1-'1';
end if;
else newtime0<=oldtime0-'1';
end if;
end
subsec_submin;procedure addhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector)is begin
if(oldhour0=“1001”)then
newhour0<=“0000”;
newhour1<=oldhour1+'1';
else newhour0<=oldhour0+'1';
end if;
if oldhour0=“0011” and oldhour1=“0010”then
newhour0<=“0000”;newhour1<=“0000”;
end if;
end
addhour;procedure subhour(oldhour0,oldhour1:in std_logic_vector;
signal newhour0:out std_logic_vector;
signal newhour1:out std_logic_vector)is begin if oldhour0=“0000” then
newhour1<=oldhour1-'1';newhour0<=“1001”;
else newhour0<=oldhour0-'1';
end if;
if oldhour0=“0000” and oldhour1=“0000”then
newhour0<=“0011”;newhour1<=“0010”;
end if;
end
subhour;end pac;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity second_wave is
Port(f1000 : in std_logic;
second_wave1 : buffer std_logic);end second_wave;
architecture Behavioral of second_wave is signal cnt:std_logic_vector(8 downto 0);begin
process(f1000,cnt)
begin
if rising_edge(f1000)then
if(cnt=“111110011”)then
cnt<=“000000000”;second_wave1<=not second_wave1;
else cnt<=cnt+'1';
end if;
end if;
end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are--provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;
entity settime is
Port(hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);
mytime,run : in std_logic;
result : out std_logic);end settime;
architecture Behavioral of settime is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);begin p0:process(mytime)
begin
if mytime='1'then
dhour1<=hour1;
dhour0<=hour0;
dmin1<=min1;
dmin0<=min0;
dsec1<=sec1;
dsec0<=sec0;
end if;
end process p0;p1:process(run)
begin if run='1'then
if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then
result<='1';
else result<='0';
end if;else result<='0';end if;
end process p1;end Behavioral;
第三篇：51單片機(jī)c語(yǔ)言電子鐘(已加入調(diào)時(shí)、鬧鈴、整點(diǎn)報(bào)時(shí)功能)
51單片機(jī)c語(yǔ)言電子鐘（已加入調(diào)時(shí)、鬧鈴、整點(diǎn)報(bào)時(shí)功能）
效果圖：
程序如下：
//51單片機(jī)c語(yǔ)言電子鐘（已加入調(diào)時(shí)、鬧鈴、整點(diǎn)報(bào)時(shí)功能）
//WHJWNAVY 2011/10/14
#include
P2=0XDF;P0=dispcode[10];//間隔符-delay(1);
P2=0XBF;
P0=dispcode[shi%10];//時(shí)個(gè)位 delay(1);P2=0X7F;P0=dispcode[shi/10];//時(shí)十位 delay(1);}
if(P1_6==0)//設(shè)定時(shí) { delay(30);if(P1_6==0){ shi++;if(shi==24){ shi=0;} } delay(250);} if(P1_7==0)//設(shè)定分 { delay(30);
if(P1_7==0){ fen++;if(fen==60){ fen=0;} } delay(250);}
if((hour==shi)&(minite==fen)&(seconde==0))//鬧鈴時(shí)間到，報(bào)警十次。{ for(bjcs=0;bjcs<10;bjcs++){ P1_5=0;delay(500);P1_5=1;delay(500);} } }
/*主函數(shù)*/ void main(void){ P1=0XFF;TMOD = 0x11;//time0為定時(shí)器，方式1 TH0=0x3c;//預(yù)置計(jì)數(shù)初值,50ms TL0=0xb0;EA=1;//總中斷開(kāi)
ET0=1;//允許定時(shí)器0中斷 TR0=1;//開(kāi)啟定時(shí)器0 while(1){ keyscan();//按鍵掃描 dingshi();//定時(shí)鬧鐘 zhengdian();//整點(diǎn)報(bào)時(shí) display();//顯示時(shí)間 } }
void timer0(void)interrupt 1 //定時(shí)器0方式1，中斷一次 { TH0=0x3c;//手動(dòng)加載計(jì)數(shù)脈沖次數(shù)
50ms
TL0=0xb0;TMOD=0x11;mstcnt++;//用于計(jì)算時(shí)間，每隔50ms加1 if(mstcnt==20)//mstcnt滿(mǎn)20即為一秒 { seconde++;//秒+1 time_pro();//時(shí)間處理
mstcnt=0;//對(duì)計(jì)數(shù)單元的清零，重新開(kāi)始計(jì)數(shù) } }
第四篇：認(rèn)識(shí)整點(diǎn)教案
大班數(shù)學(xué)《認(rèn)識(shí)整點(diǎn)》
趙海鳳
活動(dòng)目標(biāo)：、使幼兒認(rèn)識(shí)時(shí)鐘，能叫出名稱(chēng)，基本掌握鐘面的主要結(jié)構(gòu)。2、使幼兒知道時(shí)針、分針、能正確辨認(rèn)整點(diǎn)。、培養(yǎng)幼兒的觀察力和操作能力，使幼兒建立初步的時(shí)間概念。
活動(dòng)準(zhǔn)備：
課件《認(rèn)識(shí)整點(diǎn)》、實(shí)物大鐘一個(gè)、小鐘若干、鐘面若干
一、預(yù)備活動(dòng)。
走線(xiàn)，線(xiàn)上游戲：聽(tīng)音樂(lè)一個(gè)跟著一個(gè)走隨老師做動(dòng)作。
二、集體活動(dòng)。
1、以謎語(yǔ) 一張大圓臉，沒(méi)腿也沒(méi)嘴。沒(méi)腿會(huì)走路，沒(méi)嘴能報(bào)時(shí)。引入活動(dòng)，請(qǐng)大家猜猜是什么？教師出示掛鐘，提問(wèn)：“它叫什么？家里還有哪些鐘（大座鐘，催我們?cè)缭缙鸬男◆[鐘，還有人們?yōu)榱藬y帶方便，將鐘做得很小，戴在手上，叫手表）？鐘的作用是什么？（時(shí)鐘不停地走動(dòng)，為人們顯示時(shí)間，人們按時(shí)鐘上的時(shí)間來(lái)進(jìn)行工作、學(xué)習(xí)和工作。
2.教師出示大鐘，請(qǐng)幼兒觀察鐘面。鐘面上有1—12的數(shù)字，有兩根指針，鐘上的數(shù)字“12”在上面，“6”在下面，并教幼兒認(rèn)識(shí)“時(shí)針”和“分針”的名稱(chēng)。
2.針兄弟要在圓形跑到上比賽跑，幫助幼兒認(rèn)識(shí)較短的時(shí)針和較長(zhǎng)的分針，探索分針和時(shí)針的運(yùn)動(dòng)關(guān)系。教師慢慢撥鐘，引導(dǎo)幼兒觀察分針和時(shí)針的運(yùn)動(dòng)。讓幼兒說(shuō)出：分針跑得快，時(shí)針跑得慢。通過(guò)撥鐘，引導(dǎo)幼兒認(rèn)識(shí)整點(diǎn)。教師將時(shí)針?lè)轴樁紦茉凇?2”上，然
后將長(zhǎng)針轉(zhuǎn)一圈，讓幼兒注意短針有什么變化（走了一大格或走了一個(gè)數(shù)字），教師反復(fù)撥幾次，使幼兒明白長(zhǎng)針（分針）每走一圈，短針（時(shí)針）就走一個(gè)字，這就是一個(gè)小時(shí)。
3、教師繼續(xù)撥長(zhǎng)針。邊撥邊告訴幼兒當(dāng)短針（時(shí)針）正指向某一個(gè)數(shù)字，長(zhǎng)針（分針）正指向某一個(gè)數(shù)字，長(zhǎng)針（分針）正指向12時(shí)就表示“X”點(diǎn)鐘。邊撥邊和幼兒齊說(shuō)：“一點(diǎn)鐘，兩點(diǎn)鐘，三點(diǎn)鐘..........直到十二點(diǎn)鐘”（即：兩針再次重合）為止。
4、引導(dǎo)幼兒在鐘面上撥出各個(gè)鐘點(diǎn)。老師演“狼”說(shuō)幾點(diǎn)，小羊就撥幾點(diǎn)，請(qǐng)老狼巡視看鐘。小羊撥好了鐘就定住，老狼看時(shí)間撥對(duì)了的不吃，撥錯(cuò)了就吃小羊。
5、教師根據(jù)幼兒撥鐘情況總結(jié)，沒(méi)個(gè)時(shí)間段在做什么，早上7點(diǎn)起床，上午9點(diǎn)上課，中午12點(diǎn)吃午餐，下午5點(diǎn)放學(xué)，晚上8點(diǎn)睡覺(jué)。教育幼兒從小做到按時(shí)間進(jìn)行各種活動(dòng)，珍惜時(shí)間，上學(xué)不能遲到，放學(xué)時(shí)不能在路上貪玩。
三、游戲活動(dòng)：老狼老狼幾點(diǎn)鐘。
教師手拿1－12點(diǎn)鐘面卡片走在前面。幼兒跟在“老狼”后面邊走邊問(wèn)：“老狼老狼幾點(diǎn)鐘”？“老狼”舉起1點(diǎn)鐘的卡片并回答：“1點(diǎn)鐘”。...........當(dāng)“老狼”回答“天黑了”時(shí)，其他幼兒必須快速回到座位上安靜下來(lái)，最后一個(gè)回到座位上的幼兒就被“老狼”“吃掉”，游戲反復(fù)進(jìn)行。
四、結(jié)束部分
知識(shí)拓展，引導(dǎo)幼兒了解古代的計(jì)時(shí)方法。
第五篇：認(rèn)識(shí)整點(diǎn)和半點(diǎn)
? ? ?
認(rèn)識(shí)整點(diǎn)和半點(diǎn) 活動(dòng)目標(biāo)：
1、幼兒在回憶已有經(jīng)驗(yàn)的基礎(chǔ)上，通過(guò)對(duì)鐘面的觀察與操作了解秒針、分針、時(shí)針的運(yùn)行關(guān)系。
2、認(rèn)識(shí)整點(diǎn)、半點(diǎn)及的讀法及記錄方法。
3、在活動(dòng)中誘發(fā)幼兒形成遵守時(shí)間與愛(ài)惜時(shí)間的良好習(xí)慣。
活動(dòng)準(zhǔn)備：
1、教具：有關(guān)各種時(shí)鐘的幻燈片;時(shí)鐘一面，可活動(dòng)鐘面一只;表示7、8、9、10點(diǎn)鐘的鐘面各一只，時(shí)間記錄卡各一張。
2、學(xué)具：幼兒觀察記錄表每人一份，活動(dòng)鐘面每人一份;實(shí)物時(shí)鐘4只。
活動(dòng)過(guò)程：
一、調(diào)動(dòng)已有經(jīng)驗(yàn)，回憶相關(guān)知識(shí)。
1、前段時(shí)間我們小朋友和老師一起做了有關(guān)時(shí)鐘的調(diào)查，知道時(shí)鐘有好多好多種。現(xiàn)在請(qǐng)你看看老師從網(wǎng)上下載的鐘，看看你認(rèn)識(shí)它嗎?
2、依次出示幻燈片，幼兒講名稱(chēng)。
3、剛才我們所見(jiàn)到的只是時(shí)鐘家族的一部分，它可能還有其他的種類(lèi)，我們以后再來(lái)探討。
4、上次我們已經(jīng)認(rèn)識(shí)過(guò)鐘面，來(lái)告訴大家，最長(zhǎng)的針叫(秒針)，有點(diǎn)長(zhǎng)的針叫(分針)，最短的針叫時(shí)針。鐘面上一共有多少個(gè)數(shù)字(12)，最上面的是數(shù)字12，然后依次是1、2……11。請(qǐng)你好好回憶一下，時(shí)鐘里的指針是朝哪一個(gè)方向走的?(1……12)對(duì)了，這樣的方向就叫順時(shí)針?lè)较颉?/p>
二、交流調(diào)查表，說(shuō)說(shuō)自己在什么時(shí)間，正在干什么?
1、小朋友們說(shuō)的真好，那你知道我們?nèi)藶槭裁匆褂苗妴?
2、鐘與我們?nèi)说纳钣兄芮械年P(guān)系，前幾天我們小朋友已經(jīng)做過(guò)了一個(gè)調(diào)查，將自己活動(dòng)的時(shí)間記錄了下來(lái)，現(xiàn)在請(qǐng)你拿出自己的調(diào)查表，說(shuō)說(shuō)你在什么時(shí)間在干什么?你只要說(shuō)出長(zhǎng)針在幾，短針在幾的時(shí)候，你在干什么?好我們先自己說(shuō)。
3、誰(shuí)愿意上來(lái)說(shuō)給大家聽(tīng)。(請(qǐng)3—4個(gè)小朋友上來(lái)說(shuō))。
4、說(shuō)的真好，鐘面上的指針在不停的發(fā)生著變化，它們?cè)谶\(yùn)行中有什么關(guān)系呢?
5、老師為你們準(zhǔn)備了幾個(gè)時(shí)鐘，請(qǐng)你看看里面有幾根指針，(兩根)你猜猜看是哪兩根針呢?(分針與時(shí)針)，那秒針在哪兒呢?聽(tīng)(滴答)聲就是秒針在跑。那他們兩在運(yùn)行時(shí)有什么關(guān)系呢?下面請(qǐng)我們小朋友們?nèi)ネ嬉煌妫纯此麄冎g到底有什么秘密?注意，撥指針的時(shí)候一定要按照順時(shí)針?lè)较驌堋?/p>
6、說(shuō)說(shuō)看，你們都發(fā)現(xiàn)了什么?說(shuō)的真好，分針走一圈，時(shí)針走一格，這就表示一個(gè)小時(shí)。
7、那么長(zhǎng)針、短針指著的數(shù)字又是表示幾點(diǎn)鐘呢?別急，老師來(lái)向你們介紹。
三、認(rèn)識(shí)整點(diǎn)、半點(diǎn)以及它們的記錄方法。
1、好，先請(qǐng)你們聽(tīng)一個(gè)好聽(tīng)的故事。
2、教師有表情的講述故事《小明秋游》，邊講邊出示相關(guān)時(shí)間的鐘面。
3、講述后提問(wèn)：
1)、小明去秋游了嗎?為什么沒(méi)去成?
2)、他該幾點(diǎn)鐘起床，他是幾點(diǎn)鐘起床的?
3)、小明到幼兒園是幾點(diǎn)鐘了?
4)、他為什么會(huì)遲到，他是幾點(diǎn)鐘睡覺(jué)的?
課后反思：
優(yōu)點(diǎn)：
1.創(chuàng)設(shè)情景，激發(fā)興趣。在課的開(kāi)始部分利用謎語(yǔ)和色彩鮮艷的多媒體課件激發(fā)了幼兒的興趣。
2.小組合作，探究新知。在活動(dòng)中，我采取了小組合作學(xué)習(xí)的形式，讓讓幼兒自主學(xué)習(xí)，通過(guò)觀察、比較、操作、交流等多種形式，調(diào)動(dòng)幼兒多種感官進(jìn)行合作學(xué)習(xí)，培養(yǎng)合作意識(shí)，讓幼兒體驗(yàn)成功的快樂(lè)。
3.游戲化教學(xué)，符合幼兒認(rèn)知規(guī)律。在活動(dòng)中，我運(yùn)用了多種游戲形式，如：敲一敲、師幼競(jìng)賽、拿票坐車(chē)去玩等，在游戲中幼兒進(jìn)一步認(rèn)識(shí)了鐘表，讓幼兒在游戲中獲得了發(fā)展。
4.教具、學(xué)具準(zhǔn)備充分，鐘面和實(shí)物鬧鐘達(dá)到人手一份，為幼兒創(chuàng)造了豐富的操作材料。
不足：
1.幼兒認(rèn)真傾聽(tīng)的習(xí)慣還有待加強(qiáng)培養(yǎng)。
2.教師的語(yǔ)言要注意兒童化。
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